Commit a5fce077 authored by Isaku Yamahata's avatar Isaku Yamahata Committed by Michael S. Tsirkin
Browse files

pci bridge: implement secondary bus reset 



Trigger secondary bus reset when secondary bus reset bit
value changes from 0 to 1.

Signed-off-by: default avatarIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent 9bb33586

hw/pci_bridge.c

+10 −1
Original line number Diff line number Diff line
@@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 
void pci_bridge_write_config(PCIDevice *d,

                             uint32_t address, uint32_t val, int len)

{

    PCIBridge *s = container_of(d, PCIBridge, dev);

    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    uint16_t newctl;



    pci_default_write_config(d, address, val, len);



    if (/* io base/limit */
@@ -147,9 +151,14 @@ void pci_bridge_write_config(PCIDevice *d, 
        /* memory base/limit, prefetchable base/limit and

           io base/limit upper 16 */

        ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {

        PCIBridge *s = container_of(d, PCIBridge, dev);

        pci_bridge_update_mappings(&s->sec_bus);

    }



    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {

        /* Trigger hot reset on 0->1 transition. */

        pci_bus_reset(&s->sec_bus);

    }

}



void pci_bridge_disable_base_limit(PCIDevice *dev)