Commit a566da1b authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: A64: List unsupported shift-imm opcodes 



Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
parent 931c8cc2

target-arm/translate-a64.c

+11 −2
Original line number Diff line number Diff line
@@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) 
        handle_vec_simd_sqshrn(s, true, false, is_u, is_u,

                               immh, immb, opcode, rn, rd);

        break;

    default:

    case 0x8: /* SRI */

    case 0xc: /* SQSHLU */

    case 0xe: /* SQSHL, UQSHL */

    case 0x1f: /* FCVTZS, FCVTZU */

        unsupported_encoding(s, insn);

        break;

    default:

        unallocated_encoding(s);

        break;

    }

}
@@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) 
        handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,

                                     opcode, rn, rd);

        break;

    case 0x8: /* SRI */

    case 0xc: /* SQSHLU */

    case 0xe: /* SQSHL, UQSHL */

    case 0x1f: /* FCVTZS/ FCVTZU */

        unsupported_encoding(s, insn);

        return;

    default:

        unsupported_encoding(s, insn);

        unallocated_encoding(s);

        return;

    }

}