Commit a4f667b6 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into staging 



s390x update:
- have the bios tolerate bootmap signature entries
- next chunk of vector instruction support in tcg
- a headers update against Linux 5.2-rc1
- add more facilities and gen15 machines to the cpu model

# gpg: Signature made Tue 21 May 2019 16:09:35 BST
# gpg:                using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg:                issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg:                 aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg:                 aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20190521-3: (55 commits)
  s390x/cpumodel: wire up 8561 and 8562 as gen15 machines
  s390x/cpumodel: add gen15 defintions
  s390x/cpumodel: add Deflate-conversion facility
  s390x/cpumodel: enhanced sort facility
  s390x/cpumodel: vector enhancements
  s390x/cpumodel: msa9 facility
  s390x/cpumodel: Miscellaneous-Instruction-Extensions Facility 3
  s390x/cpumodel: ignore csske for expansion
  linux headers: update against Linux 5.2-rc1
  update-linux-headers: handle new header file
  s390x/tcg: Implement VECTOR TEST UNDER MASK
  s390x/tcg: Implement VECTOR SUM ACROSS WORD
  s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD
  s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD
  s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
  s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION
  s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
  s390x/tcg: Implement VECTOR SUBTRACT
  s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *
  s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 247ba27c c657e84f

hw/s390x/css.c

+18 −4
Original line number Diff line number Diff line
@@ -830,8 +830,12 @@ static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 
    if (op == CDS_OP_A) {

        goto incr;

    }

    if (!cds->do_skip) {

        ret = address_space_rw(&address_space_memory, cds->cda,

                               MEMTXATTRS_UNSPECIFIED, buff, len, op);

    } else {

        ret = MEMTX_OK;

    }

    if (ret != MEMTX_OK) {

        cds->flags |= CDS_F_STREAM_BROKEN;

        return -EINVAL;
@@ -928,8 +932,13 @@ static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 
    do {

        iter_len = MIN(len, cont_left);

        if (op != CDS_OP_A) {

            if (!cds->do_skip) {

                ret = address_space_rw(&address_space_memory, cds->cda,

                                   MEMTXATTRS_UNSPECIFIED, buff, iter_len, op);

                                       MEMTXATTRS_UNSPECIFIED, buff, iter_len,

                                       op);

            } else {

                ret = MEMTX_OK;

            }

            if (ret != MEMTX_OK) {

                /* assume inaccessible address */

                ret = -EINVAL; /* channel program check */
@@ -968,6 +977,11 @@ void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 


    cds->count = ccw->count;

    cds->cda_orig = ccw->cda;

    /* skip is only effective for read, read backwards, or sense commands */

    cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) &&

        ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE ||

         (ccw->cmd_code & 0x03) == 0x02 /* read */ ||

         (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */);

    ccw_dstream_rewind(cds);

    if (!(cds->flags & CDS_F_IDA)) {

        cds->op_handler = ccw_dstream_rw_noflags;

hw/s390x/ipl.c

+1 −2
Original line number Diff line number Diff line
@@ -374,8 +374,7 @@ static bool s390_gen_initial_iplb(S390IPLState *ipl) 
    if (ccw_dev) {

        switch (devtype) {

        case CCW_DEVTYPE_SCSI:

            sd = (SCSIDevice *) object_dynamic_cast(OBJECT(dev_st),

                                                           TYPE_SCSI_DEVICE);

            sd = SCSI_DEVICE(dev_st);

            ipl->iplb.len = cpu_to_be32(S390_IPLB_MIN_QEMU_SCSI_LEN);

            ipl->iplb.blk0_len =

                cpu_to_be32(S390_IPLB_MIN_QEMU_SCSI_LEN - S390_IPLB_HEADER_LEN);

include/hw/s390x/css.h

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ typedef struct CcwDataStream { 
    int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,

                      CcwDataStreamOp op);

    hwaddr cda;

    bool do_skip;

} CcwDataStream;



/*

include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h

+10 −5
Original line number Diff line number Diff line
@@ -57,7 +57,8 @@ 


#define PVRDMA_ROCEV1_VERSION		17

#define PVRDMA_ROCEV2_VERSION		18

#define PVRDMA_VERSION			PVRDMA_ROCEV2_VERSION

#define PVRDMA_PPN64_VERSION		19

#define PVRDMA_VERSION			PVRDMA_PPN64_VERSION



#define PVRDMA_BOARD_ID			1

#define PVRDMA_REV_ID			1
@@ -279,8 +280,10 @@ struct pvrdma_device_shared_region { 
						/* W: Async ring page info. */

	struct pvrdma_ring_page_info cq_ring_pages;

						/* W: CQ ring page info. */

	union {

		uint32_t uar_pfn;			/* W: UAR pageframe. */

	uint32_t pad2;				/* Pad to 8-byte align. */

		uint64_t uar_pfn64;			/* W: 64-bit UAR page frame. */

	};

	struct pvrdma_device_caps caps;		/* R: Device capabilities. */

};
@@ -411,8 +414,10 @@ struct pvrdma_cmd_query_pkey_resp { 


struct pvrdma_cmd_create_uc {

	struct pvrdma_cmd_hdr hdr;

	union {

		uint32_t pfn; /* UAR page frame number */

	uint8_t reserved[4];

		uint64_t pfn64; /* 64-bit UAR page frame number */

	};

};



struct pvrdma_cmd_create_uc_resp {

include/standard-headers/drm/drm_fourcc.h

+113 −1
Original line number Diff line number Diff line
@@ -143,6 +143,17 @@ extern "C" { 
#define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */

#define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */



/*

 * Floating point 64bpp RGB

 * IEEE 754-2008 binary16 half-precision float

 * [15:0] sign:exponent:mantissa 1:5:10

 */

#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */

#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */



#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */

#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */



/* packed YCbCr */

#define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */

#define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
@@ -151,6 +162,28 @@ extern "C" { 


#define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */

#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */

#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */

#define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */



/*

 * packed Y2xx indicate for each component, xx valid data occupy msb

 * 16-xx padding occupy lsb

 */

#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */

#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */

#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */



/*

 * packed Y4xx indicate for each component, xx valid data occupy msb

 * 16-xx padding occupy lsb except Y410

 */

#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */

#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */

#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */



#define DRM_FORMAT_XVYU2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */

#define DRM_FORMAT_XVYU12_16161616	fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */

#define DRM_FORMAT_XVYU16161616	fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */



/*

 * packed YCbCr420 2x2 tiled formats
@@ -166,6 +199,15 @@ extern "C" { 
/* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */

#define DRM_FORMAT_X0L2		fourcc_code('X', '0', 'L', '2')



/*

 * 1-plane YUV 4:2:0

 * In these formats, the component ordering is specified (Y, followed by U

 * then V), but the exact Linear layout is undefined.

 * These formats can only be used with a non-Linear modifier.

 */

#define DRM_FORMAT_YUV420_8BIT	fourcc_code('Y', 'U', '0', '8')

#define DRM_FORMAT_YUV420_10BIT	fourcc_code('Y', 'U', '1', '0')



/*

 * 2 plane RGB + A

 * index 0 = RGB plane, same format as the corresponding non _A8 format has
@@ -194,6 +236,34 @@ extern "C" { 
#define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */

#define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */



/*

 * 2 plane YCbCr MSB aligned

 * index 0 = Y plane, [15:0] Y:x [10:6] little endian

 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian

 */

#define DRM_FORMAT_P210		fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */



/*

 * 2 plane YCbCr MSB aligned

 * index 0 = Y plane, [15:0] Y:x [10:6] little endian

 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian

 */

#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */



/*

 * 2 plane YCbCr MSB aligned

 * index 0 = Y plane, [15:0] Y:x [12:4] little endian

 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian

 */

#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */



/*

 * 2 plane YCbCr MSB aligned

 * index 0 = Y plane, [15:0] Y little endian

 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian

 */

#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */



/*

 * 3 plane YCbCr

 * index 0: Y plane, [7:0] Y
@@ -237,6 +307,8 @@ extern "C" { 
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06

#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07

#define DRM_FORMAT_MOD_VENDOR_ARM     0x08

#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09



/* add more to the end as needed */



#define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
@@ -571,6 +643,9 @@ extern "C" { 
 * AFBC has several features which may be supported and/or used, which are

 * represented using bits in the modifier. Not all combinations are valid,

 * and different devices or use-cases may support different combinations.

 *

 * Further information on the use of AFBC modifiers can be found in

 * Documentation/gpu/afbc.rst

 */

#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)	fourcc_mod_code(ARM, __afbc_mode)
@@ -580,10 +655,18 @@ extern "C" { 
 * Indicates the superblock size(s) used for the AFBC buffer. The buffer

 * size (in pixels) must be aligned to a multiple of the superblock size.

 * Four lowest significant bits(LSBs) are reserved for block size.

 *

 * Where one superblock size is specified, it applies to all planes of the

 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,

 * the first applies to the Luma plane and the second applies to the Chroma

 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).

 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.

 */

#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf

#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)

#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)

#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4      (3ULL)

#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)



/*

 * AFBC lossless colorspace transform
@@ -643,6 +726,35 @@ extern "C" { 
 */

#define AFBC_FORMAT_MOD_SC      (1ULL <<  9)



/*

 * AFBC double-buffer

 *

 * Indicates that the buffer is allocated in a layout safe for front-buffer

 * rendering.

 */

#define AFBC_FORMAT_MOD_DB      (1ULL << 10)



/*

 * AFBC buffer content hints

 *

 * Indicates that the buffer includes per-superblock content hints.

 */

#define AFBC_FORMAT_MOD_BCH     (1ULL << 11)



/*

 * Allwinner tiled modifier

 *

 * This tiling mode is implemented by the VPU found on all Allwinner platforms,

 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3

 * planes.

 *

 * With this tiling, the luminance samples are disposed in tiles representing

 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.

 * The pixel order in each tile is linear and the tiles are disposed linearly,

 * both in row-major order.

 */

#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)



#if defined(__cplusplus)

}

#endif