Commit a4544c45 authored by Liu Yi L's avatar Liu Yi L Committed by Michael S. Tsirkin
Browse files

intel_iommu: Use correct shift for 256 bits qi descriptor 



In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced
in VTD_IQA_REG. Software could set this bit to tell VT-d the QI descriptor
from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should
be 5 when descriptor size is 256 bits.

This patch adds the DW bit check when deciding the shift used to update
VTD_IQH_REG.

Signed-off-by: default avatarLiu Yi L <yi.l.liu@intel.com>
Message-Id: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com>
Reviewed-by: default avatarPeter Xu <peterx@redhat.com>
Acked-by: default avatarJason Wang <jasowang@redhat.com>
Cc: qemu-stable@nongnu.org
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent 9b3a35ec

hw/i386/intel_iommu.c

+6 −1
Original line number Diff line number Diff line
@@ -2549,6 +2549,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) 
/* Try to fetch and process more Invalidation Descriptors */

static void vtd_fetch_inv_desc(IntelIOMMUState *s)

{

    int qi_shift;



    /* Refer to 10.4.23 of VT-d spec 3.0 */

    qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4;



    trace_vtd_inv_qi_fetch();



    if (s->iq_tail >= s->iq_size) {
@@ -2567,7 +2572,7 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s) 
        }

        /* Must update the IQH_REG in time */

        vtd_set_quad_raw(s, DMAR_IQH_REG,

                         (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &

                         (((uint64_t)(s->iq_head)) << qi_shift) &

                         VTD_IQH_QH_MASK);

    }

}

hw/i386/intel_iommu_internal.h

+2 −1
Original line number Diff line number Diff line
@@ -230,7 +230,8 @@ 
#define VTD_IQA_DW_MASK             0x800



/* IQH_REG */

#define VTD_IQH_QH_SHIFT            4

#define VTD_IQH_QH_SHIFT_4          4

#define VTD_IQH_QH_SHIFT_5          5

#define VTD_IQH_QH_MASK             0x7fff0ULL



/* ICS_REG */