Commit a390284b authored by Samuel Damashek's avatar Samuel Damashek Committed by Richard Henderson
Browse files

cputlb: Add address parameter to VICTIM_TLB_HIT 



[rth: Split out from the original patch.]

Signed-off-by: default avatarSamuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 7e9a7c50

cputlb.c

+2 −2
Original line number Diff line number Diff line
@@ -523,9 +523,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, 
}



/* Macro to call the above, with local variables from the use context.  */

#define VICTIM_TLB_HIT(TY) \

#define VICTIM_TLB_HIT(TY, ADDR) \

  victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \

                 addr & TARGET_PAGE_MASK)

                 (ADDR) & TARGET_PAGE_MASK)



#define MMUSUFFIX _mmu

softmmu_template.h

+5 −5
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ)) {

        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

        }
@@ -235,7 +235,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ)) {

        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

        }
@@ -345,7 +345,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write)) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
@@ -415,7 +415,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write)) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
@@ -477,7 +477,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 
    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        /* TLB entry is for a different page */

        if (!VICTIM_TLB_HIT(addr_write)) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

        }

    }