Commit a31a7475 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 



Three patches to fix ExtINT for the QEMU implementation of the local APIC.

# gpg: Signature made Mon 24 Nov 2014 13:38:36 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  apic: fix incorrect handling of ExtINT interrupts wrt processor priority
  apic: fix loss of IPI due to masked ExtINT
  apic: avoid getting out of halted state on masked PIC interrupts

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0e88f478 5224c88d

hw/intc/apic.c

+12 −8
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ void apic_deliver_pic_intr(DeviceState *dev, int level) 
            apic_reset_bit(s->irr, lvt & 0xff);

            /* fall through */

        case APIC_DM_EXTINT:

            cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);

            apic_update_irq(s);

            break;

        }

    }
@@ -349,6 +349,11 @@ static int apic_get_arb_pri(APICCommonState *s) 
static int apic_irq_pending(APICCommonState *s)

{

    int irrv, ppr;



    if (!(s->spurious_vec & APIC_SV_ENABLE)) {

        return 0;

    }



    irrv = get_highest_priority_int(s->irr);

    if (irrv < 0) {

        return 0;
@@ -366,14 +371,13 @@ static void apic_update_irq(APICCommonState *s) 
{

    CPUState *cpu;



    if (!(s->spurious_vec & APIC_SV_ENABLE)) {

        return;

    }

    cpu = CPU(s->cpu);

    if (!qemu_cpu_is_self(cpu)) {

        cpu_interrupt(cpu, CPU_INTERRUPT_POLL);

    } else if (apic_irq_pending(s) > 0) {

        cpu_interrupt(cpu, CPU_INTERRUPT_HARD);

    } else if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {

        cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);

    }

}
@@ -567,7 +571,10 @@ int apic_get_interrupt(DeviceState *dev) 
    apic_sync_vapic(s, SYNC_FROM_VAPIC);

    intno = apic_irq_pending(s);



    if (intno == 0) {

    /* if there is an interrupt from the 8259, let the caller handle

     * that first since ExtINT interrupts ignore the priority.

     */

    if (intno == 0 || apic_check_pic(s)) {

        apic_sync_vapic(s, SYNC_TO_VAPIC);

        return -1;

    } else if (intno < 0) {
@@ -578,9 +585,6 @@ int apic_get_interrupt(DeviceState *dev) 
    apic_set_bit(s->isr, intno);

    apic_sync_vapic(s, SYNC_TO_VAPIC);



    /* re-inject if there is still a pending PIC interrupt */

    apic_check_pic(s);



    apic_update_irq(s);



    return intno;

target-i386/cpu.c

+8 −2
Original line number Diff line number Diff line
@@ -2912,8 +2912,14 @@ static bool x86_cpu_has_work(CPUState *cs) 
    X86CPU *cpu = X86_CPU(cs);

    CPUX86State *env = &cpu->env;



    return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |

                                      CPU_INTERRUPT_POLL)) &&

#if !defined(CONFIG_USER_ONLY)

    if (cs->interrupt_request & CPU_INTERRUPT_POLL) {

        apic_poll_irq(cpu->apic_state);

        cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);

    }

#endif



    return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&

            (env->eflags & IF_MASK)) ||

           (cs->interrupt_request & (CPU_INTERRUPT_NMI |

                                     CPU_INTERRUPT_INIT |