Commit a1f7f97b authored by Peter Maydell's avatar Peter Maydell Committed by Michael Tokarev
Browse files

hw/ppc: Avoid shifting left into sign bit 



Add U suffix to various places where we were doing "1 << 31",
which is undefined behaviour, and also to other constant
definitions in the same groups, for consistency.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarMichael Tokarev <mjt@tls.msk.ru>
parent def60298

hw/ppc/ppc.c

+1 −1
Original line number Diff line number Diff line
@@ -1002,7 +1002,7 @@ static void cpu_4xx_wdt_cb (void *opaque) 
    case 0x1:

        timer_mod(ppc40x_timer->wdt_timer, next);

        ppc40x_timer->wdt_next = next;

        env->spr[SPR_40x_TSR] |= 1 << 31;

        env->spr[SPR_40x_TSR] |= 1U << 31;

        break;

    case 0x2:

        timer_mod(ppc40x_timer->wdt_timer, next);

hw/ppc/ppc440_bamboo.c

+2 −2
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, 


    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);

    tlb->size = 1 << 31; /* up to 0x80000000  */

    tlb->size = 1U << 31; /* up to 0x80000000  */

    tlb->EPN = va & TARGET_PAGE_MASK;

    tlb->RPN = pa & TARGET_PAGE_MASK;

    tlb->PID = 0;
@@ -136,7 +136,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, 
    tlb = &env->tlb.tlbe[1];

    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);

    tlb->size = 1 << 31; /* up to 0xffffffff  */

    tlb->size = 1U << 31; /* up to 0xffffffff  */

    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;

    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;

    tlb->PID = 0;

hw/ppc/ppc4xx_devs.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) 
    uint32_t mask, sr;



    uic = opaque;

    mask = 1 << (31-irq_num);

    mask = 1U << (31-irq_num);

    LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32

                " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",

                __func__, irq_num, level,

hw/ppc/ppc_booke.c

+12 −12
Original line number Diff line number Diff line
@@ -34,15 +34,15 @@ 
/* Timer Control Register */



#define TCR_WP_SHIFT  30        /* Watchdog Timer Period */

#define TCR_WP_MASK   (0x3 << TCR_WP_SHIFT)

#define TCR_WP_MASK   (0x3U << TCR_WP_SHIFT)

#define TCR_WRC_SHIFT 28        /* Watchdog Timer Reset Control */

#define TCR_WRC_MASK  (0x3 << TCR_WRC_SHIFT)

#define TCR_WIE       (1 << 27) /* Watchdog Timer Interrupt Enable */

#define TCR_DIE       (1 << 26) /* Decrementer Interrupt Enable */

#define TCR_WRC_MASK  (0x3U << TCR_WRC_SHIFT)

#define TCR_WIE       (1U << 27) /* Watchdog Timer Interrupt Enable */

#define TCR_DIE       (1U << 26) /* Decrementer Interrupt Enable */

#define TCR_FP_SHIFT  24        /* Fixed-Interval Timer Period */

#define TCR_FP_MASK   (0x3 << TCR_FP_SHIFT)

#define TCR_FIE       (1 << 23) /* Fixed-Interval Timer Interrupt Enable */

#define TCR_ARE       (1 << 22) /* Auto-Reload Enable */

#define TCR_FP_MASK   (0x3U << TCR_FP_SHIFT)

#define TCR_FIE       (1U << 23) /* Fixed-Interval Timer Interrupt Enable */

#define TCR_ARE       (1U << 22) /* Auto-Reload Enable */



/* Timer Control Register (e500 specific fields) */
@@ -53,12 +53,12 @@ 


/* Timer Status Register  */



#define TSR_FIS       (1 << 26) /* Fixed-Interval Timer Interrupt Status */

#define TSR_DIS       (1 << 27) /* Decrementer Interrupt Status */

#define TSR_FIS       (1U << 26) /* Fixed-Interval Timer Interrupt Status */

#define TSR_DIS       (1U << 27) /* Decrementer Interrupt Status */

#define TSR_WRS_SHIFT 28        /* Watchdog Timer Reset Status */

#define TSR_WRS_MASK  (0x3 << TSR_WRS_SHIFT)

#define TSR_WIS       (1 << 30) /* Watchdog Timer Interrupt Status */

#define TSR_ENW       (1 << 31) /* Enable Next Watchdog Timer */

#define TSR_WRS_MASK  (0x3U << TSR_WRS_SHIFT)

#define TSR_WIS       (1U << 30) /* Watchdog Timer Interrupt Status */

#define TSR_ENW       (1U << 31) /* Enable Next Watchdog Timer */



typedef struct booke_timer_t booke_timer_t;

struct booke_timer_t {

hw/ppc/virtex_ml507.c

+2 −2
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, 


    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);

    tlb->size = 1 << 31; /* up to 0x80000000  */

    tlb->size = 1U << 31; /* up to 0x80000000  */

    tlb->EPN = va & TARGET_PAGE_MASK;

    tlb->RPN = pa & TARGET_PAGE_MASK;

    tlb->PID = 0;
@@ -79,7 +79,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, 
    tlb = &env->tlb.tlbe[1];

    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);

    tlb->size = 1 << 31; /* up to 0xffffffff  */

    tlb->size = 1U << 31; /* up to 0xffffffff  */

    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;

    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;

    tlb->PID = 0;