Commit a1f233f2 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE floating-point trig select coefficient 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-22-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 0762cd42

target/arm/helper-sve.h

+4 −0
Original line number Diff line number Diff line
@@ -389,6 +389,10 @@ DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) 
DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

target/arm/sve.decode

+4 −0
Original line number Diff line number Diff line
@@ -295,6 +295,10 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 
# Note esz != 0

FEXPA           00000100 .. 1 00000 101110 ..... .....          @rd_rn



# SVE floating-point trig select coefficient

# Note esz != 0

FTSSEL          00000100 .. 1 ..... 101100 ..... .....          @rd_rn_rm



### SVE Predicate Logical Operations Group



# SVE predicate logical operations

target/arm/sve_helper.c

+43 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "exec/cpu_ldst.h"

#include "exec/helper-proto.h"

#include "tcg/tcg-gvec-desc.h"

#include "fpu/softfloat.h"





/* Note that vector data is stored in host-endian 64-bit chunks,
@@ -1192,3 +1193,45 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_t desc) 
        d[i] = coeff[idx] | (exp << 52);

    }

}



void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc)

{

    intptr_t i, opr_sz = simd_oprsz(desc) / 2;

    uint16_t *d = vd, *n = vn, *m = vm;

    for (i = 0; i < opr_sz; i += 1) {

        uint16_t nn = n[i];

        uint16_t mm = m[i];

        if (mm & 1) {

            nn = float16_one;

        }

        d[i] = nn ^ (mm & 2) << 14;

    }

}



void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc)

{

    intptr_t i, opr_sz = simd_oprsz(desc) / 4;

    uint32_t *d = vd, *n = vn, *m = vm;

    for (i = 0; i < opr_sz; i += 1) {

        uint32_t nn = n[i];

        uint32_t mm = m[i];

        if (mm & 1) {

            nn = float32_one;

        }

        d[i] = nn ^ (mm & 2) << 30;

    }

}



void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc)

{

    intptr_t i, opr_sz = simd_oprsz(desc) / 8;

    uint64_t *d = vd, *n = vn, *m = vm;

    for (i = 0; i < opr_sz; i += 1) {

        uint64_t nn = n[i];

        uint64_t mm = m[i];

        if (mm & 1) {

            nn = float64_one;

        }

        d[i] = nn ^ (mm & 2) << 62;

    }

}

target/arm/translate-sve.c

+21 −0
Original line number Diff line number Diff line
@@ -953,6 +953,27 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn) 
    return true;

}



static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)

{

    static gen_helper_gvec_3 * const fns[4] = {

        NULL,

        gen_helper_sve_ftssel_h,

        gen_helper_sve_ftssel_s,

        gen_helper_sve_ftssel_d,

    };

    if (a->esz == 0) {

        return false;

    }

    if (sve_access_check(s)) {

        unsigned vsz = vec_full_reg_size(s);

        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),

                           vec_full_reg_offset(s, a->rn),

                           vec_full_reg_offset(s, a->rm),

                           vsz, vsz, 0, fns[a->esz]);

    }

    return true;

}



/*

 *** SVE Predicate Logical Operations Group

 */