Commit a1ba125c authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: A64: Register VBAR_EL3 



Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-24-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent d42e3c26

target-arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ typedef struct CPUARMState { 
        uint32_t c9_pmuserenr; /* perf monitor user enable */

        uint32_t c9_pminten; /* perf monitor interrupt enables */

        uint64_t mair_el1;

        uint64_t vbar_el[3]; /* vector base address register */

        uint64_t vbar_el[4]; /* vector base address register */

        uint32_t c13_fcse; /* FCSE PID.  */

        uint64_t contextidr_el1; /* Context ID.  */

        uint64_t tpidr_el0; /* User RW Thread register.  */

target-arm/helper.c

+5 −0
Original line number Diff line number Diff line
@@ -2138,6 +2138,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { 
      .type = ARM_CP_NO_MIGRATE,

      .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },

    { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .writefn = vbar_write,

      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),

      .resetvalue = 0 },

    REGINFO_SENTINEL

};