Loading target/arm/cpu.h +0 −1 Original line number Diff line number Diff line Loading @@ -261,7 +261,6 @@ typedef struct CPUARMState { uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ uint64_t vtimer; /* Timer tick when vcpu is stopped */ /* System control coprocessor (cp15) */ struct { Loading target/arm/machine.c +0 −1 Original line number Diff line number Diff line Loading @@ -814,7 +814,6 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), VMSTATE_UINT64(env.vtimer, ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), { Loading Loading
target/arm/cpu.h +0 −1 Original line number Diff line number Diff line Loading @@ -261,7 +261,6 @@ typedef struct CPUARMState { uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ uint64_t vtimer; /* Timer tick when vcpu is stopped */ /* System control coprocessor (cp15) */ struct { Loading
target/arm/machine.c +0 −1 Original line number Diff line number Diff line Loading @@ -814,7 +814,6 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), VMSTATE_UINT64(env.vtimer, ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), { Loading