Commit a0032cc5 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make 'any' CPU just an alias for 'max' 



Now we have a working '-cpu max', the linux-user-only
'any' CPU is pretty much the same thing, so implement it
that way.

For the moment we don't add any of the extra feature bits
to the system-emulation "max", because we don't set the
ID register bits we would need to to advertise those
features as present.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 20180308130626.12393-5-peter.maydell@linaro.org
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
parent bab52d4b

target/arm/cpu.c

+27 −23
Original line number Diff line number Diff line
@@ -970,9 +970,19 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 
    ObjectClass *oc;

    char *typename;

    char **cpuname;

    const char *cpunamestr;



    cpuname = g_strsplit(cpu_model, ",", 1);

    typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);

    cpunamestr = cpuname[0];

#ifdef CONFIG_USER_ONLY

    /* For backwards compatibility usermode emulation allows "-cpu any",

     * which has the same semantics as "-cpu max".

     */

    if (!strcmp(cpunamestr, "any")) {

        cpunamestr = "max";

    }

#endif

    typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);

    oc = object_class_by_name(typename);

    g_strfreev(cpuname);

    g_free(typename);
@@ -1716,17 +1726,10 @@ static void arm_max_initfn(Object *obj) 
        kvm_arm_set_cpu_features_from_host(cpu);

    } else {

        cortex_a15_initfn(obj);

        /* In future we might add feature bits here even if the

         * real-world A15 doesn't implement them.

         */

    }

}

#endif



#ifdef CONFIG_USER_ONLY

static void arm_any_initfn(Object *obj)

{

    ARMCPU *cpu = ARM_CPU(obj);

        /* We don't set these in system emulation mode for the moment,

         * since we don't correctly set the ID registers to advertise them,

         */

        set_feature(&cpu->env, ARM_FEATURE_V8);

        set_feature(&cpu->env, ARM_FEATURE_VFP4);

        set_feature(&cpu->env, ARM_FEATURE_NEON);
@@ -1738,7 +1741,8 @@ static void arm_any_initfn(Object *obj) 
        set_feature(&cpu->env, ARM_FEATURE_CRC);

        set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

        set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

    cpu->midr = 0xffffffff;

#endif

    }

}

#endif
@@ -1794,7 +1798,7 @@ static const ARMCPUInfo arm_cpus[] = { 
    { .name = "max",         .initfn = arm_max_initfn },

#endif

#ifdef CONFIG_USER_ONLY

    { .name = "any",         .initfn = arm_any_initfn },

    { .name = "any",         .initfn = arm_max_initfn },

#endif

#endif

    { .name = NULL }

target/arm/cpu64.c

+28 −31
Original line number Diff line number Diff line
@@ -228,17 +228,13 @@ static void aarch64_max_initfn(Object *obj) 
        kvm_arm_set_cpu_features_from_host(cpu);

    } else {

        aarch64_a57_initfn(obj);

        /* In future we might add feature bits here even if the

         * real-world A57 doesn't implement them.

         */

    }

}



#ifdef CONFIG_USER_ONLY

static void aarch64_any_initfn(Object *obj)

{

    ARMCPU *cpu = ARM_CPU(obj);



        /* We don't set these in system emulation mode for the moment,

         * since we don't correctly set the ID registers to advertise them,

         * and in some cases they're only available in AArch64 and not AArch32,

         * whereas the architecture requires them to be present in both if

         * present in either.

         */

        set_feature(&cpu->env, ARM_FEATURE_V8);

        set_feature(&cpu->env, ARM_FEATURE_VFP4);

        set_feature(&cpu->env, ARM_FEATURE_NEON);
@@ -255,10 +251,14 @@ static void aarch64_any_initfn(Object *obj) 
        set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

        set_feature(&cpu->env, ARM_FEATURE_V8_FP16);

        set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

        /* For usermode -cpu max we can use a larger and more efficient DCZ

         * blocksize since we don't have to follow what the hardware does.

         */

        cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */

        cpu->dcz_blocksize = 7; /*  512 bytes */

}

#endif

    }

}



typedef struct ARMCPUInfo {

    const char *name;
@@ -270,9 +270,6 @@ static const ARMCPUInfo aarch64_cpus[] = { 
    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },

    { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },

    { .name = "max",                .initfn = aarch64_max_initfn },

#ifdef CONFIG_USER_ONLY

    { .name = "any",         .initfn = aarch64_any_initfn },

#endif

    { .name = NULL }

};