Loading hw/ide/cmd646.c +2 −6 Original line number Diff line number Diff line Loading @@ -179,12 +179,8 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num, register_ioport_read(addr, 4, 1, bmdma_readb_1, d); } register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4); ioport_register(&bm->addr_ioport); addr += 8; } } Loading hw/ide/internal.h +2 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ */ #include <hw/ide.h> #include "block_int.h" #include "iorange.h" /* debug IDE devices */ //#define DEBUG_IDE Loading Loading @@ -496,6 +497,7 @@ struct BMDMAState { QEMUIOVector qiov; int64_t sector_num; uint32_t nsector; IORange addr_ioport; QEMUBH *bh; }; Loading hw/ide/pci.c +18 −53 Original line number Diff line number Diff line Loading @@ -73,72 +73,37 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) } } uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) static void bmdma_addr_read(IORange *ioport, uint64_t addr, unsigned width, uint64_t *data) { BMDMAState *bm = opaque; uint32_t val; val = (bm->addr >> ((addr & 3) * 8)) & 0xff; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); uint32_t mask = (1ULL << (width * 8)) - 1; void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; int shift = (addr & 3) * 8; *data = (bm->addr >> (addr * 8)) & mask; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); printf("%s: 0x%08x\n", __func__, (unsigned)*data); #endif bm->addr &= ~(0xFF << shift); bm->addr |= ((val & 0xFF) << shift) & ~3; bm->cur_addr = bm->addr; } uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) static void bmdma_addr_write(IORange *ioport, uint64_t addr, unsigned width, uint64_t data) { BMDMAState *bm = opaque; uint32_t val; val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); int shift = addr * 8; uint32_t mask = (1ULL << (width * 8)) - 1; void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; int shift = (addr & 3) * 8; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); printf("%s: 0x%08x\n", __func__, (unsigned)data); #endif bm->addr &= ~(0xFFFF << shift); bm->addr |= ((val & 0xFFFF) << shift) & ~3; bm->addr &= ~(mask << shift); bm->addr |= ((data & mask) << shift) & ~3; bm->cur_addr = bm->addr; } uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) { BMDMAState *bm = opaque; uint32_t val; val = bm->addr; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif bm->addr = val & ~3; bm->cur_addr = bm->addr; } const IORangeOps bmdma_addr_ioport_ops = { .read = bmdma_addr_read, .write = bmdma_addr_write, }; static bool ide_bmdma_current_needed(void *opaque) { Loading hw/ide/pci.h +1 −6 Original line number Diff line number Diff line Loading @@ -11,12 +11,7 @@ typedef struct PCIIDEState { } PCIIDEState; void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readb(void *opaque, uint32_t addr); void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readw(void *opaque, uint32_t addr); void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readl(void *opaque, uint32_t addr); void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val); extern const IORangeOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table); extern const VMStateDescription vmstate_ide_pci; Loading hw/ide/piix.c +2 −6 Original line number Diff line number Diff line Loading @@ -85,12 +85,8 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num, register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); register_ioport_read(addr, 4, 1, bmdma_readb, bm); register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4); ioport_register(&bm->addr_ioport); addr += 8; } } Loading Loading
hw/ide/cmd646.c +2 −6 Original line number Diff line number Diff line Loading @@ -179,12 +179,8 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num, register_ioport_read(addr, 4, 1, bmdma_readb_1, d); } register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4); ioport_register(&bm->addr_ioport); addr += 8; } } Loading
hw/ide/internal.h +2 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ */ #include <hw/ide.h> #include "block_int.h" #include "iorange.h" /* debug IDE devices */ //#define DEBUG_IDE Loading Loading @@ -496,6 +497,7 @@ struct BMDMAState { QEMUIOVector qiov; int64_t sector_num; uint32_t nsector; IORange addr_ioport; QEMUBH *bh; }; Loading
hw/ide/pci.c +18 −53 Original line number Diff line number Diff line Loading @@ -73,72 +73,37 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) } } uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) static void bmdma_addr_read(IORange *ioport, uint64_t addr, unsigned width, uint64_t *data) { BMDMAState *bm = opaque; uint32_t val; val = (bm->addr >> ((addr & 3) * 8)) & 0xff; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); uint32_t mask = (1ULL << (width * 8)) - 1; void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; int shift = (addr & 3) * 8; *data = (bm->addr >> (addr * 8)) & mask; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); printf("%s: 0x%08x\n", __func__, (unsigned)*data); #endif bm->addr &= ~(0xFF << shift); bm->addr |= ((val & 0xFF) << shift) & ~3; bm->cur_addr = bm->addr; } uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) static void bmdma_addr_write(IORange *ioport, uint64_t addr, unsigned width, uint64_t data) { BMDMAState *bm = opaque; uint32_t val; val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); int shift = addr * 8; uint32_t mask = (1ULL << (width * 8)) - 1; void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; int shift = (addr & 3) * 8; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); printf("%s: 0x%08x\n", __func__, (unsigned)data); #endif bm->addr &= ~(0xFFFF << shift); bm->addr |= ((val & 0xFFFF) << shift) & ~3; bm->addr &= ~(mask << shift); bm->addr |= ((data & mask) << shift) & ~3; bm->cur_addr = bm->addr; } uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) { BMDMAState *bm = opaque; uint32_t val; val = bm->addr; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif return val; } void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; #ifdef DEBUG_IDE printf("%s: 0x%08x\n", __func__, val); #endif bm->addr = val & ~3; bm->cur_addr = bm->addr; } const IORangeOps bmdma_addr_ioport_ops = { .read = bmdma_addr_read, .write = bmdma_addr_write, }; static bool ide_bmdma_current_needed(void *opaque) { Loading
hw/ide/pci.h +1 −6 Original line number Diff line number Diff line Loading @@ -11,12 +11,7 @@ typedef struct PCIIDEState { } PCIIDEState; void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readb(void *opaque, uint32_t addr); void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readw(void *opaque, uint32_t addr); void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val); uint32_t bmdma_addr_readl(void *opaque, uint32_t addr); void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val); extern const IORangeOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table); extern const VMStateDescription vmstate_ide_pci; Loading
hw/ide/piix.c +2 −6 Original line number Diff line number Diff line Loading @@ -85,12 +85,8 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num, register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); register_ioport_read(addr, 4, 1, bmdma_readb, bm); register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4); ioport_register(&bm->addr_ioport); addr += 8; } } Loading