Commit 9f2d175d authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

update Linux headers to 4.16-rc5 



Note that VIRTIO_GPU_CAPSET_VIRGL2 was added manually so it has to be added
manually after re-running scripts/update-linux-headers.sh.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent fb5fff15

include/standard-headers/linux/input-event-codes.h

+1 −0
Original line number Diff line number Diff line
@@ -594,6 +594,7 @@ 
#define BTN_DPAD_RIGHT		0x223



#define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */

#define KEY_ROTATE_LOCK_TOGGLE	0x231	/* Display rotation lock */



#define KEY_BUTTONCONFIG		0x240	/* AL Button Configuration */

#define KEY_TASKMANAGER		0x241	/* AL Task/Project Manager */

include/standard-headers/linux/input.h

+11 −0
Original line number Diff line number Diff line
@@ -18,10 +18,21 @@ 


/*

 * The event structure itself

 * Note that __USE_TIME_BITS64 is defined by libc based on

 * application's request to use 64 bit time_t.

 */



struct input_event {

#if (HOST_LONG_BITS != 32 || !defined(__USE_TIME_BITS64)) && !defined(__KERNEL)

	struct timeval time;

#define input_event_sec time.tv_sec

#define input_event_usec time.tv_usec

#else

	__kernel_ulong_t __sec;

	__kernel_ulong_t __usec;

#define input_event_sec  __sec

#define input_event_usec __usec

#endif

	uint16_t type;

	uint16_t code;

	int32_t value;

include/standard-headers/linux/pci_regs.h

+18 −12
Original line number Diff line number Diff line
@@ -622,15 +622,19 @@ 
 * safely.

 */

#define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */

#define  PCI_EXP_DEVCAP2_COMP_TMOUT_DIS	0x00000010 /* Completion Timeout Disable supported */

#define  PCI_EXP_DEVCAP2_ARI		0x00000020 /* Alternative Routing-ID */

#define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE	0x00000040 /* Atomic Op routing */

#define PCI_EXP_DEVCAP2_ATOMIC_COMP64	0x00000100 /* Atomic 64-bit compare */

#define  PCI_EXP_DEVCAP2_ATOMIC_COMP32	0x00000080 /* 32b AtomicOp completion */

#define  PCI_EXP_DEVCAP2_ATOMIC_COMP64	0x00000100 /* 64b AtomicOp completion */

#define  PCI_EXP_DEVCAP2_ATOMIC_COMP128	0x00000200 /* 128b AtomicOp completion */

#define  PCI_EXP_DEVCAP2_LTR		0x00000800 /* Latency tolerance reporting */

#define  PCI_EXP_DEVCAP2_OBFF_MASK	0x000c0000 /* OBFF support mechanism */

#define  PCI_EXP_DEVCAP2_OBFF_MSG	0x00040000 /* New message signaling */

#define  PCI_EXP_DEVCAP2_OBFF_WAKE	0x00080000 /* Re-use WAKE# for OBFF */

#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */

#define  PCI_EXP_DEVCTL2_COMP_TIMEOUT	0x000f	/* Completion Timeout Value */

#define  PCI_EXP_DEVCTL2_COMP_TMOUT_DIS	0x0010	/* Completion Timeout Disable */

#define  PCI_EXP_DEVCTL2_ARI		0x0020	/* Alternative Routing-ID */

#define PCI_EXP_DEVCTL2_ATOMIC_REQ	0x0040	/* Set Atomic requests */

#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
@@ -966,26 +970,28 @@ 


/* Downstream Port Containment */

#define PCI_EXP_DPC_CAP			4	/* DPC Capability */

#define PCI_EXP_DPC_IRQ			0x1f	/* DPC Interrupt Message Number */

#define  PCI_EXP_DPC_CAP_RP_EXT		0x20	/* Root Port Extensions for DPC */

#define  PCI_EXP_DPC_CAP_POISONED_TLP	0x40	/* Poisoned TLP Egress Blocking Supported */

#define  PCI_EXP_DPC_CAP_SW_TRIGGER	0x80	/* Software Triggering Supported */

#define  PCI_EXP_DPC_RP_PIO_LOG_SIZE	0xF00	/* RP PIO log size */

#define PCI_EXP_DPC_IRQ			0x001F	/* Interrupt Message Number */

#define  PCI_EXP_DPC_CAP_RP_EXT		0x0020	/* Root Port Extensions */

#define  PCI_EXP_DPC_CAP_POISONED_TLP	0x0040	/* Poisoned TLP Egress Blocking Supported */

#define  PCI_EXP_DPC_CAP_SW_TRIGGER	0x0080	/* Software Triggering Supported */

#define  PCI_EXP_DPC_RP_PIO_LOG_SIZE	0x0F00	/* RP PIO Log Size */

#define  PCI_EXP_DPC_CAP_DL_ACTIVE	0x1000	/* ERR_COR signal on DL_Active supported */



#define PCI_EXP_DPC_CTL			6	/* DPC control */

#define  PCI_EXP_DPC_CTL_EN_NONFATAL 	0x02	/* Enable trigger on ERR_NONFATAL message */

#define  PCI_EXP_DPC_CTL_INT_EN 	0x08	/* DPC Interrupt Enable */

#define  PCI_EXP_DPC_CTL_EN_NONFATAL 	0x0002	/* Enable trigger on ERR_NONFATAL message */

#define  PCI_EXP_DPC_CTL_INT_EN 	0x0008	/* DPC Interrupt Enable */



#define PCI_EXP_DPC_STATUS		8	/* DPC Status */

#define  PCI_EXP_DPC_STATUS_TRIGGER	0x01	/* Trigger Status */

#define  PCI_EXP_DPC_STATUS_INTERRUPT	0x08	/* Interrupt Status */

#define  PCI_EXP_DPC_RP_BUSY		0x10	/* Root Port Busy */

#define  PCI_EXP_DPC_STATUS_TRIGGER	    0x0001 /* Trigger Status */

#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN	    0x0006 /* Trigger Reason */

#define  PCI_EXP_DPC_STATUS_INTERRUPT	    0x0008 /* Interrupt Status */

#define  PCI_EXP_DPC_RP_BUSY		    0x0010 /* Root Port Busy */

#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */



#define PCI_EXP_DPC_SOURCE_ID		10	/* DPC Source Identifier */



#define PCI_EXP_DPC_RP_PIO_STATUS	 0x0C	/* RP PIO Status */

#define PCI_EXP_DPC_RP_PIO_MASK		 0x10	/* RP PIO MASK */

#define PCI_EXP_DPC_RP_PIO_MASK		 0x10	/* RP PIO Mask */

#define PCI_EXP_DPC_RP_PIO_SEVERITY	 0x14	/* RP PIO Severity */

#define PCI_EXP_DPC_RP_PIO_SYSERROR	 0x18	/* RP PIO SysError */

#define PCI_EXP_DPC_RP_PIO_EXCEPTION	 0x1C	/* RP PIO Exception */

include/standard-headers/linux/virtio_net.h

+13 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
					 * Steering */

#define VIRTIO_NET_F_CTRL_MAC_ADDR 23	/* Set MAC address */



#define VIRTIO_NET_F_SPEED_DUPLEX 63	/* Device set linkspeed and duplex */



#ifndef VIRTIO_NET_NO_LEGACY

#define VIRTIO_NET_F_GSO	6	/* Host handles pkts w/ any GSO type */

#endif /* VIRTIO_NET_NO_LEGACY */
@@ -76,6 +78,17 @@ struct virtio_net_config { 
	uint16_t max_virtqueue_pairs;

	/* Default maximum transmit unit advice */

	uint16_t mtu;

	/*

	 * speed, in units of 1Mb. All values 0 to INT_MAX are legal.

	 * Any other value stands for unknown.

	 */

	uint32_t speed;

	/*

	 * 0x00 - half duplex

	 * 0x01 - full duplex

	 * Any other value stands for unknown.

	 */

	uint8_t duplex;

} QEMU_PACKED;



/*

include/standard-headers/linux/virtio_ring.h

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ struct vring_avail { 
	__virtio16 ring[];

};



/* u32 is used here for ids for padding reasons. */

/* uint32_t is used here for ids for padding reasons. */

struct vring_used_elem {

	/* Index of start of used descriptor chain. */

	__virtio32 id;