Commit 9d6b9db1 authored Feb 06, 2018 by Peter Xu Committed by Michael S. Tsirkin Feb 08, 2018

pci/bus: let it has higher migration priority

In the past, we prioritized IOMMU migration so that we have such a
priority order:

    IOMMU > PCI Devices

When migrating a guest with both vIOMMU and a pcie-root-port, we'll
always migrate vIOMMU first, since pci buses will be seen to have the
same priority of general PCI devices.

That's problematic.

The thing is that PCI bus number information is stored in the root port,
and that is needed by vIOMMU during post_load(), e.g., to figure out
context entry for a device.  If we don't have correct bus numbers for
devices, we won't be able to recover device state of the DMAR memory
regions, and things will be messed up.

So let's boost the PCIe root ports to be even with higher priority:

   PCIe Root Port > IOMMU > PCI Devices

A smoke test shows that this patch fixes bug 1538953.

Also, apply this rule to all the PCI bus/bridge devices: ioh3420,
xio3130_downstream, xio3130_upstream, pcie_pci_bridge, pci-pci bridge,
i82801b11.

I noted that we set pcie_pci_bridge_dev_vmstate twice.  Clean that up
together.

CC: Alex Williamson <alex.williamson@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Dr. David Alan Gilbert <dgilbert@redhat.com>
CC: Juan Quintela <quintela@redhat.com>
CC: Laurent Vivier <lvivier@redhat.com>
Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1538953


Reported-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

parent ed247f40

hw/pci-bridge/gen_pcie_root_port.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -101,6 +101,7 @@ static void gen_rp_realize(DeviceState dev, Error *errp)

		static const VMStateDescription vmstate_rp_dev = {
		.name = "pcie-root-port",
		.priority = MIG_PRI_PCI_BUS,
		.version_id = 1,
		.minimum_version_id = 1,
		.post_load = pcie_cap_slot_post_load,

hw/pci-bridge/i82801b11.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -80,6 +80,7 @@ err_bridge:

		static const VMStateDescription i82801b11_bridge_dev_vmstate = {
		.name = "i82801b11_bridge",
		.priority = MIG_PRI_PCI_BUS,
		.fields = (VMStateField[]) {
		VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
		VMSTATE_END_OF_LIST()

hw/pci-bridge/ioh3420.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -83,6 +83,7 @@ static void ioh3420_interrupts_uninit(PCIDevice *d)

		static const VMStateDescription vmstate_ioh3420 = {
		.name = "ioh-3240-express-root-port",
		.priority = MIG_PRI_PCI_BUS,
		.version_id = 1,
		.minimum_version_id = 1,
		.post_load = pcie_cap_slot_post_load,

hw/pci-bridge/pci_bridge_dev.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -174,6 +174,7 @@ static bool pci_device_shpc_present(void *opaque, int version_id)

		static const VMStateDescription pci_bridge_dev_vmstate = {
		.name = "pci_bridge",
		.priority = MIG_PRI_PCI_BUS,
		.fields = (VMStateField[]) {
		VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
		SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),

hw/pci-bridge/pcie_pci_bridge.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -129,6 +129,7 @@ static Property pcie_pci_bridge_dev_properties[] = {

		static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
		.name = TYPE_PCIE_PCI_BRIDGE_DEV,
		.priority = MIG_PRI_PCI_BUS,
		.fields = (VMStateField[]) {
		VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
		SHPC_VMSTATE(shpc, PCIDevice, NULL),
		@@ -178,7 +179,6 @@ static void pcie_pci_bridge_class_init(ObjectClass klass, void data)
		k->config_write = pcie_pci_bridge_write_config;
		dc->vmsd = &pcie_pci_bridge_dev_vmstate;
		dc->props = pcie_pci_bridge_dev_properties;
		dc->vmsd = &pcie_pci_bridge_dev_vmstate;
		dc->reset = &pcie_pci_bridge_reset;
		set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
		hc->plug = pcie_pci_bridge_hotplug_cb;