Commit 9d1bab33 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Implement HCR.DC 



The HCR.DC virtualization configuration register bit has the
following effects:
 * SCTLR.M behaves as if it is 0 for all purposes except
   direct reads of the bit
 * HCR.VM behaves as if it is 1 for all purposes except
   direct reads of the bit
 * the memory type produced by the first stage of the EL1&EL0
   translation regime is Normal Non-Shareable,
   Inner Write-Back Read-Allocate Write-Allocate,
   Outer Write-Back Read-Allocate Write-Allocate.

Implement this behaviour.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-5-peter.maydell@linaro.org
parent b4ab8ce9

target/arm/helper.c

+21 −2
Original line number Diff line number Diff line
@@ -2303,13 +2303,15 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 
         * * The Non-secure TTBCR.EAE bit is set to 1

         * * The implementation includes EL2, and the value of HCR.VM is 1

         *

         * (Note that HCR.DC makes HCR.VM behave as if it is 1.)

         *

         * ATS1Hx always uses the 64bit format (not supported yet).

         */

        format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);



        if (arm_feature(env, ARM_FEATURE_EL2)) {

            if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {

                format64 |= env->cp15.hcr_el2 & HCR_VM;

                format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);

            } else {

                format64 |= arm_current_el(env) == 2;

            }
@@ -8718,7 +8720,8 @@ static inline bool regime_translation_disabled(CPUARMState *env, 
    }



    if (mmu_idx == ARMMMUIdx_S2NS) {

        return (env->cp15.hcr_el2 & HCR_VM) == 0;

        /* HCR.DC means HCR.VM behaves as 1 */

        return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;

    }



    if (env->cp15.hcr_el2 & HCR_TGE) {
@@ -8728,6 +8731,12 @@ static inline bool regime_translation_disabled(CPUARMState *env, 
        }

    }



    if ((env->cp15.hcr_el2 & HCR_DC) &&

        (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) {

        /* HCR.DC means SCTLR_EL1.M behaves as 0 */

        return true;

    }



    return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;

}
@@ -10708,6 +10717,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, 


            /* Combine the S1 and S2 cache attributes, if needed */

            if (!ret && cacheattrs != NULL) {

                if (env->cp15.hcr_el2 & HCR_DC) {

                    /*

                     * HCR.DC forces the first stage attributes to

                     *  Normal Non-Shareable,

                     *  Inner Write-Back Read-Allocate Write-Allocate,

                     *  Outer Write-Back Read-Allocate Write-Allocate.

                     */

                    cacheattrs->attrs = 0xff;

                    cacheattrs->shareability = 0;

                }

                *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);

            }