Loading cpu-exec.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ void cpu_loop_exit(void) longjmp(env->jmp_env, 1); } #endif #ifndef TARGET_SPARC #if !(defined(TARGET_SPARC) || defined(TARGET_SH4)) #define reg_T2 #endif Loading gdbstub.c +12 −2 Original line number Diff line number Diff line Loading @@ -504,7 +504,12 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) int i; #define SAVE(x) *ptr++=tswapl(x) for (i = 0; i < 16; i++) SAVE(env->gregs[i]); if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); } else { for (i = 0; i < 8; i++) SAVE(env->gregs[i]); } for (i = 8; i < 16; i++) SAVE(env->gregs[i]); SAVE (env->pc); SAVE (env->pr); SAVE (env->gbr); Loading @@ -527,7 +532,12 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) int i; #define LOAD(x) (x)=*ptr++; for (i = 0; i < 16; i++) LOAD(env->gregs[i]); if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); } else { for (i = 0; i < 8; i++) LOAD(env->gregs[i]); } for (i = 8; i < 16; i++) LOAD(env->gregs[i]); LOAD (env->pc); LOAD (env->pr); LOAD (env->gbr); Loading linux-user/main.c +7 −7 Original line number Diff line number Diff line Loading @@ -1370,14 +1370,14 @@ void cpu_loop (CPUState *env) switch (trapnr) { case 0x160: ret = do_syscall(env, env->gregs[0x13], env->gregs[0x14], env->gregs[0x15], env->gregs[0x16], env->gregs[0x17], env->gregs[0x10], env->gregs[3], env->gregs[4], env->gregs[5], env->gregs[6], env->gregs[7], env->gregs[0], 0); env->gregs[0x10] = ret; env->gregs[0] = ret; env->pc += 2; break; case EXCP_DEBUG: Loading target-sh4/cpu.h +3 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,9 @@ #define FPSCR_PR (1 << 19) #define FPSCR_DN (1 << 18) #define DELAY_SLOT (1 << 0) #define DELAY_SLOT (1 << 0) /* Must be the same as SR_T. */ /* This flag is set if the next insn is a delay slot for a conditional jump. The dynamic value of the DELAY_SLOT determines whether the jup is taken. */ #define DELAY_SLOT_CONDITIONAL (1 << 1) /* Those are used in contexts only */ #define BRANCH (1 << 2) Loading target-sh4/exec.h +1 −1 Original line number Diff line number Diff line Loading @@ -26,7 +26,7 @@ register struct CPUSH4State *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); //register uint32_t T2 asm(AREG3); #define FT0 (env->ft0) #define FT1 (env->ft1) Loading Loading
cpu-exec.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ void cpu_loop_exit(void) longjmp(env->jmp_env, 1); } #endif #ifndef TARGET_SPARC #if !(defined(TARGET_SPARC) || defined(TARGET_SH4)) #define reg_T2 #endif Loading
gdbstub.c +12 −2 Original line number Diff line number Diff line Loading @@ -504,7 +504,12 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) int i; #define SAVE(x) *ptr++=tswapl(x) for (i = 0; i < 16; i++) SAVE(env->gregs[i]); if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); } else { for (i = 0; i < 8; i++) SAVE(env->gregs[i]); } for (i = 8; i < 16; i++) SAVE(env->gregs[i]); SAVE (env->pc); SAVE (env->pr); SAVE (env->gbr); Loading @@ -527,7 +532,12 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) int i; #define LOAD(x) (x)=*ptr++; for (i = 0; i < 16; i++) LOAD(env->gregs[i]); if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); } else { for (i = 0; i < 8; i++) LOAD(env->gregs[i]); } for (i = 8; i < 16; i++) LOAD(env->gregs[i]); LOAD (env->pc); LOAD (env->pr); LOAD (env->gbr); Loading
linux-user/main.c +7 −7 Original line number Diff line number Diff line Loading @@ -1370,14 +1370,14 @@ void cpu_loop (CPUState *env) switch (trapnr) { case 0x160: ret = do_syscall(env, env->gregs[0x13], env->gregs[0x14], env->gregs[0x15], env->gregs[0x16], env->gregs[0x17], env->gregs[0x10], env->gregs[3], env->gregs[4], env->gregs[5], env->gregs[6], env->gregs[7], env->gregs[0], 0); env->gregs[0x10] = ret; env->gregs[0] = ret; env->pc += 2; break; case EXCP_DEBUG: Loading
target-sh4/cpu.h +3 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,9 @@ #define FPSCR_PR (1 << 19) #define FPSCR_DN (1 << 18) #define DELAY_SLOT (1 << 0) #define DELAY_SLOT (1 << 0) /* Must be the same as SR_T. */ /* This flag is set if the next insn is a delay slot for a conditional jump. The dynamic value of the DELAY_SLOT determines whether the jup is taken. */ #define DELAY_SLOT_CONDITIONAL (1 << 1) /* Those are used in contexts only */ #define BRANCH (1 << 2) Loading
target-sh4/exec.h +1 −1 Original line number Diff line number Diff line Loading @@ -26,7 +26,7 @@ register struct CPUSH4State *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); //register uint32_t T2 asm(AREG3); #define FT0 (env->ft0) #define FT1 (env->ft1) Loading