Commit 9b964318 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

target-microblaze: Introduce a use-hw-mul property 



Introduce a use-div property making multiplication instructions
optional.

Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 47709e4c

target/microblaze/cpu.c

+8 −4
Original line number Diff line number Diff line
@@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    qemu_init_vcpu(cs);



    env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \

                       | PVR0_USE_EXC_MASK \

    env->pvr.regs[0] = PVR0_USE_EXC_MASK \

                       | PVR0_USE_ICACHE_MASK \

                       | PVR0_USE_DCACHE_MASK;

    env->pvr.regs[2] = PVR2_D_OPB_MASK \
@@ -160,8 +159,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
                        | PVR2_I_LMB_MASK \

                        | PVR2_USE_MSR_INSTR \

                        | PVR2_USE_PCMP_INSTR \

                        | PVR2_USE_HW_MUL_MASK \

                        | PVR2_USE_MUL64_MASK \

                        | PVR2_FPU_EXC_MASK \

                        | 0;
@@ -178,6 +175,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |

                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |

                        (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |

                        (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |

                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
@@ -187,6 +185,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |

                        (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |

                        (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |

                        (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |

                        (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0);
@@ -235,6 +235,10 @@ static Property mb_properties[] = { 
     *                  are enabled

     */

    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),

    /* If use-hw-mul > 0 - Multiplier is enabled

     * If use-hw-mul = 2 - 64-bit multiplier is enabled

     */

    DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),

    DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),

    DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),

    DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),

target/microblaze/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -298,6 +298,7 @@ struct MicroBlazeCPU { 
        bool stackprot;

        uint32_t base_vectors;

        uint8_t use_fpu;

        uint8_t use_hw_mul;

        bool use_barrel;

        bool use_div;

        bool use_mmu;

target/microblaze/translate.c

+2 −3
Original line number Diff line number Diff line
@@ -589,7 +589,7 @@ static void dec_mul(DisasContext *dc) 


    if ((dc->tb_flags & MSR_EE_FLAG)

         && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)

         && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {

         && !dc->cpu->cfg.use_hw_mul) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(dc, EXCP_HW_EXCP);

        return;
@@ -604,8 +604,7 @@ static void dec_mul(DisasContext *dc) 
    }



    /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2.  */

    if (subcode >= 1 && subcode <= 3

        && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_MUL64_MASK))) {

    if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) {

        /* nop??? */

    }