Commit 9a9f1f59 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Clear SVE high bits for FMOV 



Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.

Cc: qemu-stable@nongnu.org
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180502221552.3873-5-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 88808a02

target/arm/translate-a64.c

+5 −12
Original line number Diff line number Diff line
@@ -5681,31 +5681,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) 


    if (itof) {

        TCGv_i64 tcg_rn = cpu_reg(s, rn);

        TCGv_i64 tmp;



        switch (type) {

        case 0:

        {

            /* 32 bit */

            TCGv_i64 tmp = tcg_temp_new_i64();

            tmp = tcg_temp_new_i64();

            tcg_gen_ext32u_i64(tmp, tcg_rn);

            tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));

            tcg_gen_movi_i64(tmp, 0);

            tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));

            write_fp_dreg(s, rd, tmp);

            tcg_temp_free_i64(tmp);

            break;

        }

        case 1:

        {

            /* 64 bit */

            TCGv_i64 tmp = tcg_const_i64(0);

            tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));

            tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));

            tcg_temp_free_i64(tmp);

            write_fp_dreg(s, rd, tcg_rn);

            break;

        }

        case 2:

            /* 64 bit to top half. */

            tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));

            clear_vec_high(s, true, rd);

            break;

        }

    } else {