Commit 9a562ae7 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

target/sh4: introduce DELAY_SLOT_MASK 



This will make easier the introduction of a new flag in the next
patches.

Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 73479c5c

target/sh4/cpu.h

+2 −1
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
#define FPSCR_RM_NEAREST       (0 << 0)

#define FPSCR_RM_ZERO          (1 << 0)



#define DELAY_SLOT_MASK        0x3

#define DELAY_SLOT             (1 << 0)

#define DELAY_SLOT_CONDITIONAL (1 << 1)
@@ -380,7 +381,7 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, 
{

    *pc = env->pc;

    *cs_base = 0;

    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) /* Bits 0-1 */

    *flags = (env->flags & DELAY_SLOT_MASK)                    /* Bits  0- 1 */

            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */

            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */

            | (env->sr & (1u << SR_FD))                        /* Bit 15 */

target/sh4/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -172,11 +172,11 @@ void superh_cpu_do_interrupt(CPUState *cs) 
    env->sgr = env->gregs[15];

    env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);



    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {

    if (env->flags & DELAY_SLOT_MASK) {

        /* Branch instruction should be executed again before delay slot. */

	env->spc -= 2;

	/* Clear flags for exception/interrupt routine. */

        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);

        env->flags &= ~DELAY_SLOT_MASK;

    }



    if (do_exp) {

target/sh4/translate.c

+8 −9
Original line number Diff line number Diff line
@@ -217,8 +217,7 @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) 
    if (ctx->delayed_pc != (uint32_t) -1) {

        tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);

    }

    if ((ctx->tbflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))

        != ctx->envflags) {

    if ((ctx->tbflags & DELAY_SLOT_MASK) != ctx->envflags) {

        tcg_gen_movi_i32(cpu_flags, ctx->envflags);

    }

}
@@ -329,7 +328,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) 
#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */



#define CHECK_NOT_DELAY_SLOT \

    if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {     \

    if (ctx->envflags & DELAY_SLOT_MASK) {                           \

        gen_save_cpu_state(ctx, true);                               \

        gen_helper_raise_slot_illegal_instruction(cpu_env);          \

        ctx->bstate = BS_EXCP;                                       \
@@ -339,7 +338,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) 
#define CHECK_PRIVILEGED                                             \

    if (IS_USER(ctx)) {                                              \

        gen_save_cpu_state(ctx, true);                               \

        if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \

        if (ctx->envflags & DELAY_SLOT_MASK) {                       \

            gen_helper_raise_slot_illegal_instruction(cpu_env);      \

        } else {                                                     \

            gen_helper_raise_illegal_instruction(cpu_env);           \
@@ -351,7 +350,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) 
#define CHECK_FPU_ENABLED                                            \

    if (ctx->tbflags & (1u << SR_FD)) {                              \

        gen_save_cpu_state(ctx, true);                               \

        if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \

        if (ctx->envflags & DELAY_SLOT_MASK) {                       \

            gen_helper_raise_slot_fpu_disable(cpu_env);              \

        } else {                                                     \

            gen_helper_raise_fpu_disable(cpu_env);                   \
@@ -1784,7 +1783,7 @@ static void _decode_opc(DisasContext * ctx) 
    fflush(stderr);

#endif

    gen_save_cpu_state(ctx, true);

    if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {

    if (ctx->envflags & DELAY_SLOT_MASK) {

        gen_helper_raise_slot_illegal_instruction(cpu_env);

    } else {

        gen_helper_raise_illegal_instruction(cpu_env);
@@ -1798,9 +1797,9 @@ static void decode_opc(DisasContext * ctx) 


    _decode_opc(ctx);



    if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {

    if (old_flags & DELAY_SLOT_MASK) {

        /* go out of the delay slot */

        ctx->envflags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);

        ctx->envflags &= ~DELAY_SLOT_MASK;

        tcg_gen_movi_i32(cpu_flags, ctx->envflags);

        ctx->bstate = BS_BRANCH;

        if (old_flags & DELAY_SLOT_CONDITIONAL) {
@@ -1824,7 +1823,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) 
    pc_start = tb->pc;

    ctx.pc = pc_start;

    ctx.tbflags = (uint32_t)tb->flags;

    ctx.envflags = tb->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL);

    ctx.envflags = tb->flags & DELAY_SLOT_MASK;

    ctx.bstate = BS_NONE;

    ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;

    /* We don't know if the delayed pc came from a dynamic or static branch,