Unverified Commit 9a2551ed authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_test: Add reset functionality 



This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent df42fdd6

hw/riscv/sifive_test.c

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "hw/hw.h"

#include "hw/sysbus.h"

#include "qemu/module.h"

#include "sysemu/runstate.h"

#include "target/riscv/cpu.h"

#include "hw/hw.h"

#include "hw/riscv/sifive_test.h"
@@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr, 
            exit(code);

        case FINISHER_PASS:

            exit(0);

        case FINISHER_RESET:

            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

            return;

        default:

            break;

        }

include/hw/riscv/sifive_test.h

+2 −1
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ typedef struct SiFiveTestState { 


enum {

    FINISHER_FAIL = 0x3333,

    FINISHER_PASS = 0x5555

    FINISHER_PASS = 0x5555,

    FINISHER_RESET = 0x7777

};



DeviceState *sifive_test_create(hwaddr addr);