Commit 9a183916 authored by Hervé Poussineau's avatar Hervé Poussineau Committed by Andreas Färber
Browse files

raven: Implement non-contiguous I/O region 



Remove now duplicated code from prep board.

Signed-off-by: default avatarHervé Poussineau <hpoussin@reactos.org>
Signed-off-by: default avatarAndreas Färber <andreas.faerber@web.de>
parent 49a4e212

hw/pci-host/prep.c

+85 −0
Original line number Diff line number Diff line
@@ -54,8 +54,12 @@ typedef struct PRePPCIState { 


    qemu_irq irq[PCI_NUM_PINS];

    PCIBus pci_bus;

    AddressSpace pci_io_as;

    MemoryRegion pci_io_non_contiguous;

    MemoryRegion pci_intack;

    RavenPCIState pci_dev;



    int contiguous_map;

} PREPPCIState;



#define BIOS_SIZE (1024 * 1024)
@@ -107,6 +111,71 @@ static const MemoryRegionOps PPC_intack_ops = { 
    },

};



static inline hwaddr raven_io_address(PREPPCIState *s,

                                      hwaddr addr)

{

    if (s->contiguous_map == 0) {

        /* 64 KB contiguous space for IOs */

        addr &= 0xFFFF;

    } else {

        /* 8 MB non-contiguous space for IOs */

        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);

    }



    /* FIXME: handle endianness switch */



    return addr;

}



static uint64_t raven_io_read(void *opaque, hwaddr addr,

                              unsigned int size)

{

    PREPPCIState *s = opaque;

    uint8_t buf[4];



    addr = raven_io_address(s, addr);

    address_space_read(&s->pci_io_as, addr, buf, size);



    if (size == 1) {

        return buf[0];

    } else if (size == 2) {

        return lduw_p(buf);

    } else if (size == 4) {

        return ldl_p(buf);

    } else {

        g_assert_not_reached();

    }

}



static void raven_io_write(void *opaque, hwaddr addr,

                           uint64_t val, unsigned int size)

{

    PREPPCIState *s = opaque;

    uint8_t buf[4];



    addr = raven_io_address(s, addr);



    if (size == 1) {

        buf[0] = val;

    } else if (size == 2) {

        stw_p(buf, val);

    } else if (size == 4) {

        stl_p(buf, val);

    } else {

        g_assert_not_reached();

    }



    address_space_write(&s->pci_io_as, addr, buf, size);

}



static const MemoryRegionOps raven_io_ops = {

    .read = raven_io_read,

    .write = raven_io_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .impl.max_access_size = 4,

    .valid.unaligned = true,

};



static int prep_map_irq(PCIDevice *pci_dev, int irq_num)

{

    return (irq_num + (pci_dev->devfn >> 3)) & 1;
@@ -119,6 +188,13 @@ static void prep_set_irq(void *opaque, int irq_num, int level) 
    qemu_set_irq(pic[irq_num] , level);

}



static void raven_change_gpio(void *opaque, int n, int level)

{

    PREPPCIState *s = opaque;



    s->contiguous_map = level;

}



static void raven_pcihost_realizefn(DeviceState *d, Error **errp)

{

    SysBusDevice *dev = SYS_BUS_DEVICE(d);
@@ -133,6 +209,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) 
        sysbus_init_irq(dev, &s->irq[i]);

    }



    qdev_init_gpio_in(d, raven_change_gpio, 1);



    pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);



    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
@@ -164,6 +242,13 @@ static void raven_pcihost_initfn(Object *obj) 
    MemoryRegion *address_space_io = get_system_io();

    DeviceState *pci_dev;



    memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,

                          "pci-io-non-contiguous", 0x00800000);

    address_space_init(&s->pci_io_as, get_system_io(), "raven-io");



    /* CPU address space */

    memory_region_add_subregion_overlap(address_space_mem, 0x80000000,

                                        &s->pci_io_non_contiguous, 1);

    pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,

                        address_space_mem, address_space_io, 0, TYPE_PCI_BUS);

    h->bus = &s->pci_bus;

hw/ppc/prep.c

+3 −91
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ typedef struct sysctrl_t { 
    uint8_t state;

    uint8_t syscontrol;

    int contiguous_map;

    qemu_irq contiguous_map_irq;

    int endian;

} sysctrl_t;
@@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 
    case 0x0850:

        /* I/O map type register */

        sysctrl->contiguous_map = val & 0x01;

        qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);

        break;

    default:

        printf("ERROR: unaffected IO port write: %04" PRIx32
@@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 
    return retval;

}



static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,

                                                 hwaddr addr)

{

    if (sysctrl->contiguous_map == 0) {

        /* 64 KB contiguous space for IOs */

        addr &= 0xFFFF;

    } else {

        /* 8 MB non-contiguous space for IOs */

        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);

    }



    return addr;

}



static void PPC_prep_io_writeb (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    cpu_outb(addr, value);

}



static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inb(addr);



    return ret;

}



static void PPC_prep_io_writew (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);

    cpu_outw(addr, value);

}



static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inw(addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);



    return ret;

}



static void PPC_prep_io_writel (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);

    cpu_outl(addr, value);

}



static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inl(addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);



    return ret;

}



static const MemoryRegionOps PPC_prep_io_ops = {

    .old_mmio = {

        .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },

        .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

};



#define NVRAM_SIZE        0x2000
@@ -458,7 +375,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
    CPUPPCState *env = NULL;

    nvram_t nvram;

    M48t59State *m48t59;

    MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);

    PortioList *port_list = g_new(PortioList, 1);

#if 0

    MemoryRegion *xcsr = g_new(MemoryRegion, 1);
@@ -567,6 +483,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
        fprintf(stderr, "Couldn't create PCI host controller.\n");

        exit(1);

    }

    sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);



    /* PCI -> ISA bridge */

    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
@@ -587,11 +504,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
    qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */

    qdev_init_nofail(dev);



    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */

    memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl,

                          "ppc-io", 0x00800000);

    memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);



    /* init basic PC hardware */

    pci_vga_init(pci_bus);