Commit 999b9416 authored by Jin Guojie's avatar Jin Guojie Committed by Richard Henderson
Browse files

tcg-mips: Adjust calling conventions for mips64 



Tested-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Tested-by: default avatarJames Hogan <james.hogan@imgtec.com>
Tested-by: default avatarYunQiang Su <wzssyqa@gmail.com>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarJin Guojie <jinguojie@loongson.cn>
Message-Id: <1483592275-4496-10-git-send-email-jinguojie@loongson.cn>
parent 98d69076

tcg/mips/tcg-target.h

+15 −4
Original line number Diff line number Diff line
@@ -27,7 +27,14 @@ 
#ifndef MIPS_TCG_TARGET_H

#define MIPS_TCG_TARGET_H



#if _MIPS_SIM == _ABIO32

# define TCG_TARGET_REG_BITS 32

#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64

# define TCG_TARGET_REG_BITS 64

#else

# error "Unknown ABI"

#endif



#define TCG_TARGET_INSN_UNIT_SIZE 4

#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16

#define TCG_TARGET_NB_REGS 32
@@ -71,8 +78,12 @@ typedef enum { 
} TCGReg;



/* used for function call generation */

#define TCG_TARGET_STACK_ALIGN 8

#define TCG_TARGET_STACK_ALIGN        16

#if _MIPS_SIM == _ABIO32

# define TCG_TARGET_CALL_STACK_OFFSET 16

#else

# define TCG_TARGET_CALL_STACK_OFFSET 0

#endif

#define TCG_TARGET_CALL_ALIGN_ARGS    1



/* MOVN/MOVZ instructions detection */

tcg/mips/tcg-target.inc.c

+15 −6
Original line number Diff line number Diff line
@@ -91,10 +91,6 @@ static const int tcg_target_reg_alloc_order[] = { 
    TCG_REG_S8,



    /* Call clobbered registers.  */

    TCG_REG_T0,

    TCG_REG_T1,

    TCG_REG_T2,

    TCG_REG_T3,

    TCG_REG_T4,

    TCG_REG_T5,

    TCG_REG_T6,
@@ -105,17 +101,27 @@ static const int tcg_target_reg_alloc_order[] = { 
    TCG_REG_V0,



    /* Argument registers, opposite order of allocation.  */

    TCG_REG_T3,

    TCG_REG_T2,

    TCG_REG_T1,

    TCG_REG_T0,

    TCG_REG_A3,

    TCG_REG_A2,

    TCG_REG_A1,

    TCG_REG_A0,

};



static const TCGReg tcg_target_call_iarg_regs[4] = {

static const TCGReg tcg_target_call_iarg_regs[] = {

    TCG_REG_A0,

    TCG_REG_A1,

    TCG_REG_A2,

    TCG_REG_A3

    TCG_REG_A3,

#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64

    TCG_REG_T0,

    TCG_REG_T1,

    TCG_REG_T2,

    TCG_REG_T3,

#endif

};



static const TCGReg tcg_target_call_oarg_regs[2] = {
@@ -2427,6 +2433,9 @@ static void tcg_target_init(TCGContext *s) 
{

    tcg_target_detect_isa();

    tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);

    if (TCG_TARGET_REG_BITS == 64) {

        tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff);

    }

    tcg_regset_set(tcg_target_call_clobber_regs,

                   (1 << TCG_REG_V0) |

                   (1 << TCG_REG_V1) |