Loading target/xtensa/cpu.h +5 −4 Original line number Diff line number Diff line Loading @@ -280,14 +280,15 @@ enum { LEVEL1_INTERRUPT_CAUSE, ALLOCA_CAUSE, INTEGER_DIVIDE_BY_ZERO_CAUSE, PRIVILEGED_CAUSE = 8, PC_VALUE_ERROR_CAUSE, PRIVILEGED_CAUSE, LOAD_STORE_ALIGNMENT_CAUSE, INSTR_PIF_DATA_ERROR_CAUSE = 12, EXTERNAL_REG_PRIVILEGE_CAUSE, EXCLUSIVE_ERROR_CAUSE, INSTR_PIF_DATA_ERROR_CAUSE, LOAD_STORE_PIF_DATA_ERROR_CAUSE, INSTR_PIF_ADDR_ERROR_CAUSE, LOAD_STORE_PIF_ADDR_ERROR_CAUSE, INST_TLB_MISS_CAUSE, INST_TLB_MULTI_HIT_CAUSE, INST_FETCH_PRIVILEGE_CAUSE, Loading Loading
target/xtensa/cpu.h +5 −4 Original line number Diff line number Diff line Loading @@ -280,14 +280,15 @@ enum { LEVEL1_INTERRUPT_CAUSE, ALLOCA_CAUSE, INTEGER_DIVIDE_BY_ZERO_CAUSE, PRIVILEGED_CAUSE = 8, PC_VALUE_ERROR_CAUSE, PRIVILEGED_CAUSE, LOAD_STORE_ALIGNMENT_CAUSE, INSTR_PIF_DATA_ERROR_CAUSE = 12, EXTERNAL_REG_PRIVILEGE_CAUSE, EXCLUSIVE_ERROR_CAUSE, INSTR_PIF_DATA_ERROR_CAUSE, LOAD_STORE_PIF_DATA_ERROR_CAUSE, INSTR_PIF_ADDR_ERROR_CAUSE, LOAD_STORE_PIF_ADDR_ERROR_CAUSE, INST_TLB_MISS_CAUSE, INST_TLB_MULTI_HIT_CAUSE, INST_FETCH_PRIVILEGE_CAUSE, Loading