Commit 97ed5ccd authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Richard Henderson
Browse files

tlb: Add "ifetch" argument to cpu_mmu_index() 



This is set to true when the index is for an instruction fetch
translation.

The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.

All targets ignore it for now, and all other callers pass "false".

This will allow targets who wish to split the mmu index between
instruction and data accesses to do so. A subsequent patch will
do just that for PowerPC.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent ba9cef7b

cputlb.c

+1 −1
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
    CPUState *cpu = ENV_GET_CPU(env1);



    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = cpu_mmu_index(env1);

    mmu_idx = cpu_mmu_index(env1, true);

    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=

                 (addr & TARGET_PAGE_MASK))) {

        cpu_ldub_code(env1, addr);

include/exec/cpu_ldst.h

+2 −2
Original line number Diff line number Diff line
@@ -363,7 +363,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 
#endif /* (NB_MMU_MODES > 12) */



/* these access are slower, they must be as rare as possible */

#define CPU_MMU_INDEX (cpu_mmu_index(env))

#define CPU_MMU_INDEX (cpu_mmu_index(env, false))

#define MEMSUFFIX _data

#define DATA_SIZE 1

#include "exec/cpu_ldst_template.h"
@@ -379,7 +379,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 
#undef CPU_MMU_INDEX

#undef MEMSUFFIX



#define CPU_MMU_INDEX (cpu_mmu_index(env))

#define CPU_MMU_INDEX (cpu_mmu_index(env, true))

#define MEMSUFFIX _code

#define SOFTMMU_CODE_ACCESS

target-alpha/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -376,7 +376,7 @@ enum { 
    PS_USER_MODE = 8

};



static inline int cpu_mmu_index(CPUAlphaState *env)

static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)

{

    if (env->pal_mode) {

        return MMU_KERNEL_IDX;

target-alpha/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -2878,7 +2878,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 


    ctx.tb = tb;

    ctx.pc = pc_start;

    ctx.mem_idx = cpu_mmu_index(env);

    ctx.mem_idx = cpu_mmu_index(env, false);

    ctx.implver = env->implver;

    ctx.singlestep_enabled = cs->singlestep_enabled;

target-arm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -1678,7 +1678,7 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 
}



/* Determine the current mmu_idx to use for normal loads/stores */

static inline int cpu_mmu_index(CPUARMState *env)

static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)

{

    int el = arm_current_el(env);
@@ -1911,7 +1911,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 
                   << ARM_TBFLAG_XSCALE_CPAR_SHIFT);

    }



    *flags |= (cpu_mmu_index(env) << ARM_TBFLAG_MMUIDX_SHIFT);

    *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);

    /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine

     * states defined in the ARM ARM for software singlestep:

     *  SS_ACTIVE   PSTATE.SS   State