Commit 97c00c54 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

spapr/xive: Set the OS CAM line at reset 



When a Virtual Processor is scheduled to run on a HW thread, the
hypervisor pushes its identifier in the OS CAM line. When running with
kernel_irqchip=off, QEMU needs to emulate the same behavior.

Set the OS CAM line when the interrupt presenter of the sPAPR core is
reset. This will also cover the case of hot-plugged CPUs.

This change also has the benefit to remove the use of CPU_FOREACH()
which can be unsafe.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
Message-Id: <20191022163812.330-8-clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 00d6f4db

hw/intc/spapr_xive.c

+17 −31
Original line number Diff line number Diff line
@@ -205,23 +205,6 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 
    memory_region_set_enabled(&xive->end_source.esb_mmio, false);

}



/*

 * When a Virtual Processor is scheduled to run on a HW thread, the

 * hypervisor pushes its identifier in the OS CAM line. Emulate the

 * same behavior under QEMU.

 */

void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx)

{

    uint8_t  nvt_blk;

    uint32_t nvt_idx;

    uint32_t nvt_cam;



    spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx);



    nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx));

    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4);

}



static void spapr_xive_end_reset(XiveEND *end)

{

    memset(end, 0, sizeof(*end));
@@ -544,21 +527,32 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 
    }



    spapr_cpu->tctx = XIVE_TCTX(obj);



    /*

     * (TCG) Early setting the OS CAM line for hotplugged CPUs as they

     * don't beneficiate from the reset of the XIVE IRQ backend

     */

    spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);

    return 0;

}



static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam)

{

    uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam);

    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);

}



static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc,

                                     PowerPCCPU *cpu)

{

    XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;

    uint8_t  nvt_blk;

    uint32_t nvt_idx;



    xive_tctx_reset(tctx);



    /*

     * When a Virtual Processor is scheduled to run on a HW thread,

     * the hypervisor pushes its identifier in the OS CAM line.

     * Emulate the same behavior under QEMU.

     */

    spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx);



    xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx));

}



static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val)
@@ -651,14 +645,6 @@ static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 
static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp)

{

    SpaprXive *xive = SPAPR_XIVE(intc);

    CPUState *cs;



    CPU_FOREACH(cs) {

        PowerPCCPU *cpu = POWERPC_CPU(cs);



        /* (TCG) Set the OS CAM line of the thread interrupt context. */

        spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);

    }



    if (kvm_enabled()) {

        int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp);

include/hw/ppc/spapr_xive.h

+0 −1
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ typedef struct SpaprXive { 
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);



void spapr_xive_hcall_init(SpaprMachineState *spapr);

void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);

void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);

void spapr_xive_map_mmio(SpaprXive *xive);