Commit 97052d64 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging 



Patch queue for ppc - 2015-01-07

New year's release. This time's highlights:

  - E500: More RAM support
  - pseries: New SLOF release
  - Migration fixes
  - Simplify USB spawning logic, removes support for explicit usb=off
  - TCG: Simple untansactional TM emulation

# gpg: Signature made Wed 07 Jan 2015 15:19:37 GMT using RSA key ID 03FEDC60
# gpg: Good signature from "Alexander Graf <agraf@suse.de>"
# gpg:                 aka "Alexander Graf <alex@csgraf.de>"

* remotes/agraf/tags/signed-ppc-for-upstream: (37 commits)
  hw/ppc/mac_newworld: simplify usb controller creation logic
  hw/ppc/spapr: simplify usb controller creation logic
  hw/ppc/mac_newworld: QOMified mac99 machines
  hw/usb: simplified usb_enabled
  hw/machine: added machine_usb wrapper
  hw/ppc: modified the condition for usb controllers to be created for some ppc machines
  target-ppc: Cast ssize_t to size_t before printing with %zx
  target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY
  PPC: e500: Fix GPIO controller interrupt number
  target-ppc: Introduce Privileged TM Noops
  target-ppc: Introduce tcheck
  target-ppc: Introduce TM Noops
  target-ppc: Introduce tbegin
  target-ppc: Introduce TEXASRU Bit Fields
  target-ppc: Power8 Supports Transactional Memory
  target-ppc: Introduce tm_enabled Bit to CPU State
  target-ppc: Introduce Feature Flag for Transactional Memory
  target-ppc: Introduce Instruction Type for Transactional Memory
  pseries: Update SLOF firmware image to 20141202
  PPC: Fix crash on spapr_tce_table_finalize()
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents e77d927f 75c74ccb

device_tree.c

+10 −4
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt, 
    uint64_t value;

    int cellnum, vnum, ncells;

    uint32_t hival;

    int ret;



    propcells = g_new0(uint32_t, numvalues * 2);
@@ -331,18 +332,23 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt, 
    for (vnum = 0; vnum < numvalues; vnum++) {

        ncells = values[vnum * 2];

        if (ncells != 1 && ncells != 2) {

            return -1;

            ret = -1;

            goto out;

        }

        value = values[vnum * 2 + 1];

        hival = cpu_to_be32(value >> 32);

        if (ncells > 1) {

            propcells[cellnum++] = hival;

        } else if (hival != 0) {

            return -1;

            ret = -1;

            goto out;

        }

        propcells[cellnum++] = cpu_to_be32(value);

    }



    return qemu_fdt_setprop(fdt, node_path, property, propcells,

    ret = qemu_fdt_setprop(fdt, node_path, property, propcells,

                           cellnum * sizeof(uint32_t));

out:

    g_free(propcells);

    return ret;

}

hw/pci-host/ppce500.c

+107 −6
Original line number Diff line number Diff line
@@ -62,11 +62,19 @@ 
#define PPCE500_PCI_NR_POBS     5

#define PPCE500_PCI_NR_PIBS     3



#define PIWAR_EN                0x80000000      /* Enable */

#define PIWAR_PF                0x20000000      /* prefetch */

#define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */

#define PIWAR_READ_SNOOP        0x00050000

#define PIWAR_WRITE_SNOOP       0x00005000

#define PIWAR_SZ_MASK           0x0000003f



struct  pci_outbound {

    uint32_t potar;

    uint32_t potear;

    uint32_t powbar;

    uint32_t powar;

    MemoryRegion mem;

};



struct pci_inbound {
@@ -74,6 +82,7 @@ struct pci_inbound { 
    uint32_t piwbar;

    uint32_t piwbear;

    uint32_t piwar;

    MemoryRegion mem;

};



#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
@@ -91,10 +100,13 @@ struct PPCE500PCIState { 
    uint32_t irq_num[PCI_NUM_PINS];

    uint32_t first_slot;

    uint32_t first_pin_irq;

    AddressSpace bm_as;

    MemoryRegion bm;

    /* mmio maps */

    MemoryRegion container;

    MemoryRegion iomem;

    MemoryRegion pio;

    MemoryRegion busmem;

};



#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
@@ -181,6 +193,71 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, 
    return value;

}



/* DMA mapping */

static void e500_update_piw(PPCE500PCIState *pci, int idx)

{

    uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;

    uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;

    uint64_t war = pci->pib[idx].piwar;

    uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);

    MemoryRegion *address_space_mem = get_system_memory();

    MemoryRegion *mem = &pci->pib[idx].mem;

    MemoryRegion *bm = &pci->bm;

    char *name;



    if (memory_region_is_mapped(mem)) {

        /* Before we modify anything, unmap and destroy the region */

        memory_region_del_subregion(bm, mem);

        object_unparent(OBJECT(mem));

    }



    if (!(war & PIWAR_EN)) {

        /* Not enabled, nothing to do */

        return;

    }



    name = g_strdup_printf("PCI Inbound Window %d", idx);

    memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,

                             size);

    memory_region_add_subregion_overlap(bm, wbar, mem, -1);

    g_free(name);



    pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",

              __func__, size, wbar, tar);

}



/* BAR mapping */

static void e500_update_pow(PPCE500PCIState *pci, int idx)

{

    uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;

    uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;

    uint64_t war = pci->pob[idx].powar;

    uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);

    MemoryRegion *mem = &pci->pob[idx].mem;

    MemoryRegion *address_space_mem = get_system_memory();

    char *name;



    if (memory_region_is_mapped(mem)) {

        /* Before we modify anything, unmap and destroy the region */

        memory_region_del_subregion(address_space_mem, mem);

        object_unparent(OBJECT(mem));

    }



    if (!(war & PIWAR_EN)) {

        /* Not enabled, nothing to do */

        return;

    }



    name = g_strdup_printf("PCI Outbound Window %d", idx);

    memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,

                             size);

    memory_region_add_subregion(address_space_mem, wbar, mem);

    g_free(name);



    pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",

              __func__, size, wbar, tar);

}



static void pci_reg_write4(void *opaque, hwaddr addr,

                           uint64_t value, unsigned size)

{
@@ -199,18 +276,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, 
    case PPCE500_PCI_OW3:

    case PPCE500_PCI_OW4:

        idx = (addr >> 5) & 0x7;

        switch (addr & 0xC) {

        switch (addr & 0x1F) {

        case PCI_POTAR:

            pci->pob[idx].potar = value;

            e500_update_pow(pci, idx);

            break;

        case PCI_POTEAR:

            pci->pob[idx].potear = value;

            e500_update_pow(pci, idx);

            break;

        case PCI_POWBAR:

            pci->pob[idx].powbar = value;

            e500_update_pow(pci, idx);

            break;

        case PCI_POWAR:

            pci->pob[idx].powar = value;

            e500_update_pow(pci, idx);

            break;

        default:

            break;
@@ -221,18 +302,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, 
    case PPCE500_PCI_IW2:

    case PPCE500_PCI_IW1:

        idx = ((addr >> 5) & 0x3) - 1;

        switch (addr & 0xC) {

        switch (addr & 0x1F) {

        case PCI_PITAR:

            pci->pib[idx].pitar = value;

            e500_update_piw(pci, idx);

            break;

        case PCI_PIWBAR:

            pci->pib[idx].piwbar = value;

            e500_update_piw(pci, idx);

            break;

        case PCI_PIWBEAR:

            pci->pib[idx].piwbear = value;

            e500_update_piw(pci, idx);

            break;

        case PCI_PIWAR:

            pci->pib[idx].piwar = value;

            e500_update_piw(pci, idx);

            break;

        default:

            break;
@@ -349,13 +434,20 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d) 
    return 0;

}



static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,

                                            int devfn)

{

    PPCE500PCIState *s = opaque;



    return &s->bm_as;

}



static int e500_pcihost_initfn(SysBusDevice *dev)

{

    PCIHostState *h;

    PPCE500PCIState *s;

    PCIBus *b;

    int i;

    MemoryRegion *address_space_mem = get_system_memory();



    h = PCI_HOST_BRIDGE(dev);

    s = PPC_E500_PCI_HOST_BRIDGE(dev);
@@ -369,12 +461,22 @@ static int e500_pcihost_initfn(SysBusDevice *dev) 
    }



    memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);

    memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);



    /* PIO lives at the bottom of our bus space */

    memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);



    b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,

                         mpc85xx_pci_map_irq, s, address_space_mem,

                         &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);

                         mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,

                         PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);

    h->bus = b;



    /* Set up PCI view of memory */

    memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);

    memory_region_add_subregion(&s->bm, 0x0, &s->busmem);

    address_space_init(&s->bm_as, &s->bm, "pci-bm");

    pci_setup_iommu(b, e500_pcihost_set_iommu, s);



    pci_create_simple(b, 0, "e500-host-bridge");



    memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
@@ -388,7 +490,6 @@ static int e500_pcihost_initfn(SysBusDevice *dev) 
    memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);

    memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);

    sysbus_init_mmio(dev, &s->container);

    sysbus_init_mmio(dev, &s->pio);

    pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);



    return 0;

hw/ppc/e500.c

+16 −20
Original line number Diff line number Diff line
@@ -51,21 +51,16 @@ 
#define RAM_SIZES_ALIGN            (64UL << 20)



/* TODO: parameterize */

#define MPC8544_CCSRBAR_BASE       0xE0000000ULL

#define MPC8544_CCSRBAR_SIZE       0x00100000ULL

#define MPC8544_MPIC_REGS_OFFSET   0x40000ULL

#define MPC8544_MSI_REGS_OFFSET   0x41600ULL

#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL

#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL

#define MPC8544_PCI_REGS_OFFSET    0x8000ULL

#define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \

                                    MPC8544_PCI_REGS_OFFSET)

#define MPC8544_PCI_REGS_SIZE      0x1000ULL

#define MPC8544_PCI_IO             0xE1000000ULL

#define MPC8544_UTIL_OFFSET        0xe0000ULL

#define MPC8544_SPIN_BASE          0xEF000000ULL

#define MPC8XXX_GPIO_OFFSET        0x000FF000ULL

#define MPC8XXX_GPIO_IRQ           43

#define MPC8XXX_GPIO_IRQ           47



struct boot_info

{
@@ -293,12 +288,12 @@ static int ppce500_load_device_tree(MachineState *machine, 
    int len;

    uint32_t pci_ranges[14] =

        {

            0x2000000, 0x0, 0xc0000000,

            0x0, 0xc0000000,

            0x2000000, 0x0, params->pci_mmio_bus_base,

            params->pci_mmio_base >> 32, params->pci_mmio_base,

            0x0, 0x20000000,



            0x1000000, 0x0, 0x0,

            0x0, 0xe1000000,

            params->pci_pio_base >> 32, params->pci_pio_base,

            0x0, 0x10000,

        };

    QemuOpts *machine_opts = qemu_get_machine_opts();
@@ -389,7 +384,7 @@ static int ppce500_load_device_tree(MachineState *machine, 
        CPUState *cpu;

        PowerPCCPU *pcpu;

        char cpu_name[128];

        uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);

        uint64_t cpu_release_addr = params->spin_base + (i * 0x20);



        cpu = qemu_get_cpu(i);

        if (cpu == NULL) {
@@ -426,7 +421,7 @@ static int ppce500_load_device_tree(MachineState *machine, 


    qemu_fdt_add_subnode(fdt, "/aliases");

    /* XXX These should go into their respective devices' code */

    snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);

    snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);

    qemu_fdt_add_subnode(fdt, soc);

    qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");

    qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
@@ -434,7 +429,7 @@ static int ppce500_load_device_tree(MachineState *machine, 
    qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);

    qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,

                           MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,

                           params->ccsrbar_base >> 32, params->ccsrbar_base,

                           MPC8544_CCSRBAR_SIZE);

    /* XXX should contain a reasonable value */

    qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
@@ -493,7 +488,8 @@ static int ppce500_load_device_tree(MachineState *machine, 
    qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);

    qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);



    snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);

    snprintf(pci, sizeof(pci), "/pci@%llx",

             params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, pci);

    qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);

    qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
@@ -512,8 +508,10 @@ static int ppce500_load_device_tree(MachineState *machine, 
    }

    qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);

    qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,

                           MPC8544_PCI_REGS_BASE, 0, 0x1000);

    qemu_fdt_setprop_cells(fdt, pci, "reg",

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),

                           0, 0x1000);

    qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);

    qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);

    qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
@@ -841,7 +839,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) 
        irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];

        irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];

        env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;

        env->mpic_iack = MPC8544_CCSRBAR_BASE +

        env->mpic_iack = params->ccsrbar_base +

                         MPC8544_MPIC_REGS_OFFSET + 0xa0;



        ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
@@ -875,7 +873,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) 
    qdev_init_nofail(dev);

    ccsr = CCSR(dev);

    ccsr_addr_space = &ccsr->ccsr_space;

    memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,

    memory_region_add_subregion(address_space_mem, params->ccsrbar_base,

                                ccsr_addr_space);



    mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
@@ -917,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) 
    if (!pci_bus)

        printf("couldn't create PCI controller!\n");



    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);



    if (pci_bus) {

        /* Register network interfaces. */

        for (i = 0; i < nb_nics; i++) {
@@ -927,7 +923,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) 
    }



    /* Register spinning region */

    sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);

    sysbus_create_simple("e500-spin", params->spin_base, NULL);



    if (cur_base < (32 * 1024 * 1024)) {

        /* u-boot occupies memory up to 32MB, so load blobs above */

hw/ppc/e500.h

+5 −0
Original line number Diff line number Diff line
@@ -17,6 +17,11 @@ typedef struct PPCE500Params { 
    hwaddr platform_bus_size;

    int platform_bus_first_irq;

    int platform_bus_num_irqs;

    hwaddr ccsrbar_base;

    hwaddr pci_pio_base;

    hwaddr pci_mmio_base;

    hwaddr pci_mmio_bus_base;

    hwaddr spin_base;

} PPCE500Params;



void ppce500_init(MachineState *machine, PPCE500Params *params);

hw/ppc/e500plat.c

+5 −0
Original line number Diff line number Diff line
@@ -41,6 +41,11 @@ static void e500plat_init(MachineState *machine) 
        .platform_bus_size = (128ULL * 1024 * 1024),

        .platform_bus_first_irq = 5,

        .platform_bus_num_irqs = 10,

        .ccsrbar_base = 0xFE0000000ULL,

        .pci_pio_base = 0xFE1000000ULL,

        .pci_mmio_base = 0xC00000000ULL,

        .pci_mmio_bus_base = 0xE0000000ULL,

        .spin_base = 0xFEF000000ULL,

    };



    /* Older KVM versions don't support EPR which breaks guests when we announce