Commit 96d0ee7f authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Remove unreachable code in tcg_out_op and op_defs 



The INDEX_op_call case has just been obsoleted; the mov and movi
cases have not been reachable for years.  Attempt to document this
both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT.

Because of the TCG_OPF_NOT_PRESENT change, this must be done for
all targets in a single commit.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent af3cbfbe

tcg/aarch64/tcg-target.c

+3 −19
Original line number Diff line number Diff line
@@ -1268,14 +1268,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        s->tb_next_offset[a0] = tcg_current_code_size(s);

        break;



    case INDEX_op_call:

        if (const_args[0]) {

            tcg_out_call(s, (tcg_insn_unit *)(intptr_t)a0);

        } else {

            tcg_out_callr(s, a0);

        }

        break;



    case INDEX_op_br:

        tcg_out_goto_label(s, a0);

        break;
@@ -1596,13 +1588,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);

        break;



    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */

    case INDEX_op_mov_i64:

    case INDEX_op_mov_i32:

    case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */

    case INDEX_op_movi_i64:

    case INDEX_op_movi_i32:

        /* Always implemented with tcg_out_mov/i, never with tcg_out_op.  */

    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */

    default:

        /* Opcode not implemented.  */

        tcg_abort();

    }
@@ -1612,15 +1603,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
static const TCGTargetOpDef aarch64_op_defs[] = {

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },

    { INDEX_op_call, { "ri" } },

    { INDEX_op_br, { } },



    { INDEX_op_mov_i32, { "r", "r" } },

    { INDEX_op_mov_i64, { "r", "r" } },



    { INDEX_op_movi_i32, { "r" } },

    { INDEX_op_movi_i64, { "r" } },



    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },

tcg/arm/tcg-target.c

+3 −29
Original line number Diff line number Diff line
@@ -1038,17 +1038,6 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) 
    }

}



static inline void tcg_out_callr(TCGContext *s, int cond, int arg)

{

    if (use_armv5t_instructions) {

        tcg_out_blx(s, cond, arg);

    } else {

        tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,

                        TCG_REG_PC, SHIFT_IMM_LSL(0));

        tcg_out_bx(s, cond, arg);

    }

}



static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)

{

    TCGLabel *l = &s->labels[label_index];
@@ -1667,13 +1656,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        }

        s->tb_next_offset[args[0]] = tcg_current_code_size(s);

        break;

    case INDEX_op_call:

        if (const_args[0]) {

            tcg_out_call(s, (void *)args[0]);

        } else {

            tcg_out_callr(s, COND_AL, args[0]);

        }

        break;

    case INDEX_op_br:

        tcg_out_goto_label(s, COND_AL, args[0]);

        break;
@@ -1703,13 +1685,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);

        break;



    case INDEX_op_mov_i32:

        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,

                        args[0], 0, args[1], SHIFT_IMM_LSL(0));

        break;

    case INDEX_op_movi_i32:

        tcg_out_movi32(s, COND_AL, args[0], args[1]);

        break;

    case INDEX_op_movcond_i32:

        /* Constraints mean that v2 is always in the same register as dest,

         * so we only need to do "if condition passed, move v1 to dest".
@@ -1925,6 +1900,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);

        break;



    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */

    case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */

    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */

    default:

        tcg_abort();

    }
@@ -1933,12 +1911,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
static const TCGTargetOpDef arm_op_defs[] = {

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },

    { INDEX_op_call, { "ri" } },

    { INDEX_op_br, { } },



    { INDEX_op_mov_i32, { "r", "r" } },

    { INDEX_op_movi_i32, { "r" } },



    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },

tcg/i386/tcg-target.c

+5 −19
Original line number Diff line number Diff line
@@ -1746,20 +1746,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        }

        s->tb_next_offset[args[0]] = tcg_current_code_size(s);

        break;

    case INDEX_op_call:

        if (const_args[0]) {

            tcg_out_call(s, (tcg_insn_unit *)(uintptr_t)args[0]);

        } else {

            /* call *reg */

            tcg_out_modrm(s, OPC_GRP5, EXT5_CALLN_Ev, args[0]);

        }

        break;

    case INDEX_op_br:

        tcg_out_jxx(s, JCC_JMP, args[0], 0);

        break;

    case INDEX_op_movi_i32:

        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);

        break;

    OP_32_64(ld8u):

        /* Note that we can ignore REXW for the zero-extend to 64-bit.  */

        tcg_out_modrm_offset(s, OPC_MOVZBL, args[0], args[1], args[2]);
@@ -2009,9 +1998,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_setcond2(s, args, const_args);

        break;

#else /* TCG_TARGET_REG_BITS == 64 */

    case INDEX_op_movi_i64:

        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);

        break;

    case INDEX_op_ld32s_i64:

        tcg_out_modrm_offset(s, OPC_MOVSLQ, args[0], args[1], args[2]);

        break;
@@ -2068,6 +2054,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        }

        break;



    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */

    case INDEX_op_mov_i64:

    case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */

    case INDEX_op_movi_i64:

    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */

    default:

        tcg_abort();

    }
@@ -2078,10 +2069,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
static const TCGTargetOpDef x86_op_defs[] = {

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },

    { INDEX_op_call, { "ri" } },

    { INDEX_op_br, { } },

    { INDEX_op_mov_i32, { "r", "r" } },

    { INDEX_op_movi_i32, { "r" } },

    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },
@@ -2135,8 +2123,6 @@ static const TCGTargetOpDef x86_op_defs[] = { 
    { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },

    { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },

#else

    { INDEX_op_mov_i64, { "r", "r" } },

    { INDEX_op_movi_i64, { "r" } },

    { INDEX_op_ld8u_i64, { "r", "r" } },

    { INDEX_op_ld8s_i64, { "r", "r" } },

    { INDEX_op_ld16u_i64, { "r", "r" } },

tcg/ia64/tcg-target.c

+5 −35
Original line number Diff line number Diff line
@@ -865,20 +865,6 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *desc) 
                               TCG_REG_B0, disp));

}



static inline void tcg_out_callr(TCGContext *s, TCGReg addr)

{

    tcg_out_bundle(s, MmI,

                   tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),

                   tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),

                   tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,

                               TCG_REG_B6, TCG_REG_R2, 0));

    tcg_out_bundle(s, mmB,

                   tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),

                   INSN_NOP_M,

                   tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,

                               TCG_REG_B0, TCG_REG_B6));

}



static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)

{

    uint64_t imm, opc1;
@@ -2009,24 +1995,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_br:

        tcg_out_br(s, args[0]);

        break;

    case INDEX_op_call:

        if (likely(const_args[0])) {

            tcg_out_call(s, (tcg_insn_unit *)(intptr_t)args[0]);

        } else {

            tcg_out_callr(s, args[0]);

        }

        break;

    case INDEX_op_goto_tb:

        tcg_out_goto_tb(s, args[0]);

        break;



    case INDEX_op_movi_i32:

        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);

        break;

    case INDEX_op_movi_i64:

        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);

        break;



    case INDEX_op_ld8u_i32:

    case INDEX_op_ld8u_i64:

        tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
@@ -2236,6 +2208,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_qemu_st(s, args);

        break;



    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */

    case INDEX_op_mov_i64:

    case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */

    case INDEX_op_movi_i64:

    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */

    default:

        tcg_abort();

    }
@@ -2243,13 +2220,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 


static const TCGTargetOpDef ia64_op_defs[] = {

    { INDEX_op_br, { } },

    { INDEX_op_call, { "ri" } },

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },



    { INDEX_op_mov_i32, { "r", "r" } },

    { INDEX_op_movi_i32, { "r" } },



    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },
@@ -2291,9 +2264,6 @@ static const TCGTargetOpDef ia64_op_defs[] = { 
    { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },

    { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },



    { INDEX_op_mov_i64, { "r", "r" } },

    { INDEX_op_movi_i64, { "r" } },



    { INDEX_op_ld8u_i64, { "r", "r" } },

    { INDEX_op_ld8s_i64, { "r", "r" } },

    { INDEX_op_ld16u_i64, { "r", "r" } },

tcg/mips/tcg-target.c

+3 −14
Original line number Diff line number Diff line
@@ -1278,21 +1278,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_nop(s);

        s->tb_next_offset[args[0]] = tcg_current_code_size(s);

        break;

    case INDEX_op_call:

        assert(const_args[0]);

        tcg_out_call(s, (tcg_insn_unit *)(intptr_t)args[0]);

        break;

    case INDEX_op_br:

        tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, args[0]);

        break;



    case INDEX_op_mov_i32:

        tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);

        break;

    case INDEX_op_movi_i32:

        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);

        break;



    case INDEX_op_ld8u_i32:

        tcg_out_ldst(s, OPC_LBU, args[0], args[1], args[2]);

        break;
@@ -1540,6 +1529,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_qemu_st(s, args, 3);

        break;



    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */

    case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */

    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */

    default:

        tcg_abort();

    }
@@ -1548,11 +1540,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
static const TCGTargetOpDef mips_op_defs[] = {

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },

    { INDEX_op_call, { "i" } },

    { INDEX_op_br, { } },



    { INDEX_op_mov_i32, { "r", "r" } },

    { INDEX_op_movi_i32, { "r" } },

    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },