Commit 95ea69fb authored by Luwei Kang's avatar Luwei Kang Committed by Paolo Bonzini
Browse files

x86: add AVX512_4VNNIW and AVX512_4FMAPS features 



The spec can be found in Intel Software Developer Manual or in
Instruction Set Extensions Programming Reference.

Signed-off-by: default avatarPiotr Luc <piotr.luc@intel.com>
Signed-off-by: default avatarLuwei Kang <luwei.kang@intel.com>
Message-Id: <1477902446-5932-1-git-send-email-he.chen@linux.intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent d14fabd9

target-i386/cpu.c

+18 −1
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 
          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,

          CPUID_7_0_EBX_RDSEED */

#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)

#define TCG_7_0_EDX_FEATURES 0

#define TCG_APM_FEATURES 0

#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT

#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -444,6 +445,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
        .cpuid_reg = R_ECX,

        .tcg_features = TCG_7_0_ECX_FEATURES,

    },

    [FEAT_7_0_EDX] = {

        .feat_names = {

            NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

        },

        .cpuid_eax = 7,

        .cpuid_needs_ecx = true, .cpuid_ecx = 0,

        .cpuid_reg = R_EDX,

        .tcg_features = TCG_7_0_EDX_FEATURES,

    },

    [FEAT_8000_0007_EDX] = {

        .feat_names = {

            NULL, NULL, NULL, NULL,
@@ -2560,7 +2577,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
            if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {

                *ecx |= CPUID_7_0_ECX_OSPKE;

            }

            *edx = 0; /* Reserved */

            *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */

        } else {

            *eax = 0;

            *ebx = 0;

target-i386/cpu.h

+4 −0
Original line number Diff line number Diff line
@@ -443,6 +443,7 @@ typedef enum FeatureWord { 
    FEAT_1_ECX,         /* CPUID[1].ECX */

    FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */

    FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */

    FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */

    FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */

    FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */

    FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
@@ -629,6 +630,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_ECX_OSPKE    (1U << 4)

#define CPUID_7_0_ECX_RDPID    (1U << 22)



#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */



#define CPUID_XSAVE_XSAVEOPT   (1U << 0)

#define CPUID_XSAVE_XSAVEC     (1U << 1)

#define CPUID_XSAVE_XGETBV1    (1U << 2)