Commit 952760bb authored by Blue Swirl's avatar Blue Swirl
Browse files

Compile pci_host only once 



Convert pci_host_conf_register_mmio_noswap(x) to
pci_host_conf_register_mmio(x, 0).

Convert pci_host_conf_register_mmio(x) to
pci_host_conf_register_mmio(x, 1) for big endian hosts, all cases
happen to be BE.

Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent c1f63a9d

Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ user-obj-y += cutils.o cache-utils.o 
hw-obj-y =

hw-obj-y += loader.o

hw-obj-y += virtio.o virtio-console.o

hw-obj-y += fw_cfg.o pci.o pcie_host.o

hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o

hw-obj-y += watchdog.o

hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o

hw-obj-$(CONFIG_ECC) += ecc.o

Makefile.target

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ endif #CONFIG_BSD_USER 
# System emulator target

ifdef CONFIG_SOFTMMU



obj-y = vl.o monitor.o pci_host.o machine.o gdbstub.o

obj-y = vl.o monitor.o machine.o gdbstub.o

obj-y += qemu-timer.o

# virtio has to be here due to weird dependency between PCI and virtio-net.

# need to fix this properly

hw/dec_pci.c

+2 −2
Original line number Diff line number Diff line
@@ -69,8 +69,8 @@ static int pci_dec_21154_init_device(SysBusDevice *dev) 


    s = FROM_SYSBUS(DECState, dev);



    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);

    pci_mem_data = pci_host_data_register_mmio(&s->host_state);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);

    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);

    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    return 0;

hw/grackle_pci.c

+2 −2
Original line number Diff line number Diff line
@@ -108,8 +108,8 @@ static int pci_grackle_init_device(SysBusDevice *dev) 


    s = FROM_SYSBUS(GrackleState, dev);



    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);

    pci_mem_data = pci_host_data_register_mmio(&s->host_state);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);

    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);

    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

hw/pci_host.c

+51 −30
Original line number Diff line number Diff line
@@ -78,27 +78,24 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) 
    return val;

}



static void pci_host_config_write(ReadWriteHandler *handler,

static void pci_host_config_write_swap(ReadWriteHandler *handler,

                                       pcibus_t addr, uint32_t val, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, conf_handler);



    PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",

                __func__, addr, len, val);

#ifdef TARGET_WORDS_BIGENDIAN

    val = qemu_bswap_len(val, len);

#endif

    s->config_reg = val;

}



static uint32_t pci_host_config_read(ReadWriteHandler *handler,

static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,

                                          pcibus_t addr, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, conf_handler);

    uint32_t val = s->config_reg;

#ifdef TARGET_WORDS_BIGENDIAN



    val = qemu_bswap_len(val, len);

#endif

    PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",

                __func__, addr, len, val);

    return val;
@@ -125,20 +122,19 @@ static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler, 
    return val;

}



static void pci_host_data_write(ReadWriteHandler *handler,

static void pci_host_data_write_swap(ReadWriteHandler *handler,

                                     pcibus_t addr, uint32_t val, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, data_handler);

#ifdef TARGET_WORDS_BIGENDIAN



    val = qemu_bswap_len(val, len);

#endif

    PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",

                addr, len, val);

    if (s->config_reg & (1u << 31))

        pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);

}



static uint32_t pci_host_data_read(ReadWriteHandler *handler,

static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,

                                        pcibus_t addr, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, data_handler);
@@ -148,33 +144,54 @@ static uint32_t pci_host_data_read(ReadWriteHandler *handler, 
    val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);

    PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",

                addr, len, val);

#ifdef TARGET_WORDS_BIGENDIAN

    val = qemu_bswap_len(val, len);

#endif

    return val;

}



static void pci_host_data_write_noswap(ReadWriteHandler *handler,

                                       pcibus_t addr, uint32_t val, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, data_handler);

    PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",

                addr, len, val);

    if (s->config_reg & (1u << 31))

        pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);

}



static uint32_t pci_host_data_read_noswap(ReadWriteHandler *handler,

                                          pcibus_t addr, int len)

{

    PCIHostState *s = container_of(handler, PCIHostState, data_handler);

    uint32_t val;

    if (!(s->config_reg & (1 << 31)))

        return 0xffffffff;

    val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);

    PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",

                addr, len, val);

    return val;

}



static void pci_host_init(PCIHostState *s)

{

    s->conf_handler.write = pci_host_config_write;

    s->conf_handler.read = pci_host_config_read;

    s->conf_handler.write = pci_host_config_write_swap;

    s->conf_handler.read = pci_host_config_read_swap;

    s->conf_noswap_handler.write = pci_host_config_write_noswap;

    s->conf_noswap_handler.read = pci_host_config_read_noswap;

    s->data_handler.write = pci_host_data_write;

    s->data_handler.read = pci_host_data_read;

    s->data_handler.write = pci_host_data_write_swap;

    s->data_handler.read = pci_host_data_read_swap;

    s->data_noswap_handler.write = pci_host_data_write_noswap;

    s->data_noswap_handler.read = pci_host_data_read_noswap;

}



int pci_host_conf_register_mmio(PCIHostState *s)

int pci_host_conf_register_mmio(PCIHostState *s, int swap)

{

    pci_host_init(s);

    if (swap) {

        return cpu_register_io_memory_simple(&s->conf_handler);

}



int pci_host_conf_register_mmio_noswap(PCIHostState *s)

{

    pci_host_init(s);

    } else {

        return cpu_register_io_memory_simple(&s->conf_noswap_handler);

    }

}



void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)

{
@@ -182,10 +199,14 @@ void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s) 
    register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4);

}



int pci_host_data_register_mmio(PCIHostState *s)

int pci_host_data_register_mmio(PCIHostState *s, int swap)

{

    pci_host_init(s);

    if (swap) {

        return cpu_register_io_memory_simple(&s->data_handler);

    } else {

        return cpu_register_io_memory_simple(&s->data_noswap_handler);

    }

}



void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)