Commit 9473d0ec authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Handle TBI for sve scalar + int memory ops 



We still need to handle tbi for user-only when mte is inactive.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-37-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent aa13f7c3

target/arm/translate-a64.c

+1 −1
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) 
 * of the write-back address.

 */



static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)

TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)

{

    TCGv_i64 clean = new_tmp_a64(s);

#ifdef CONFIG_USER_ONLY

target/arm/translate-a64.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ TCGv_ptr get_fpstatus_ptr(bool); 
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,

                            unsigned int imms, unsigned int immr);

bool sve_access_check(DisasContext *s);

TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);

TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,

                        bool tag_checked, int log2_size);

TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,

target/arm/translate-sve.c

+4 −2
Original line number Diff line number Diff line
@@ -4587,9 +4587,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, 
     * For e.g. LD4, there are not enough arguments to pass all 4

     * registers as pointers, so encode the regno into the data field.

     * For consistency, do this even for LD1.

     * TODO: mte_n check here while callers are updated.

     */

    if (mte_n && s->mte_active[0]) {

    if (s->mte_active[0]) {

        int msz = dtype_msz(dtype);



        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
@@ -4599,7 +4598,10 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, 
        desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);

        desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz);

        desc <<= SVE_MTEDESC_SHIFT;

    } else {

        addr = clean_data_tbi(s, addr);

    }



    desc = simd_desc(vsz, vsz, zt | desc);

    t_desc = tcg_const_i32(desc);

    t_pg = tcg_temp_new_ptr();