Commit 93bf9a42 authored by Roman Kapl's avatar Roman Kapl Committed by Richard Henderson
Browse files

tcg/i386: fix vector operations on 32-bit hosts 



The TCG backend uses LOWREGMASK to get the low 3 bits of register numbers.
This was defined as no-op for 32-bit x86, with the assumption that we have
eight registers anyway. This assumption is not true once we have xmm regs.

Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes
and have overflown into other opcode fields, wreaking havoc.

To trigger these problems, you can try running the "movi d8, #0x0" AArch64
instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated,
but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2".

Fixes: 770c2fc7 ("Add vector operations")
Signed-off-by: default avatarRoman Kapl <rka@sysgo.com>
Message-Id: <20180824131734.18557-1-rka@sysgo.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent bd224fce

tcg/i386/tcg-target.inc.c

+0 −4
Original line number Diff line number Diff line
@@ -302,11 +302,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, 
    return 0;

}



#if TCG_TARGET_REG_BITS == 64

# define LOWREGMASK(x)	((x) & 7)

#else

# define LOWREGMASK(x)	(x)

#endif



#define P_EXT		0x100		/* 0x0f opcode prefix */

#define P_EXT38         0x200           /* 0x0f 0x38 opcode prefix */