Commit 931892e8 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170623' into staging 



Queued target/s390x patches

# gpg: Signature made Fri 23 Jun 2017 17:18:24 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170623:
  target/s390x: Implement idte instruction
  target/s390x: Improve heuristic for ipte
  target/s390x: Indicate and check for local tlb clearing
  target/s390x: Clean up TB flag bits
  target/s390x: Finish implementing ETF2-ENH
  target/s390x: Mark STFLE_49 facility as available
  target/s390x: Implement processor-assist insn
  target/s390x: Implement execution-hint insns
  target/s390x: Mark STFLE_53 facility as available
  target/s390x: Implement load-and-zero-rightmost-byte insns
  target/s390x: Implement load-on-condition-2 insns
  target/s390x: Mark FPSEH facility as available
  target/s390x: implement mvcos instruction
  target/s390x: change PSW_SHIFT_KEY
  target/s390x: Map existing FAC_* names to S390_FEAT_* names

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 14a7fe1a be7f28de

target/s390x/cpu.h

+31 −17
Original line number Diff line number Diff line
@@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); 
#undef PSW_MASK_WAIT

#undef PSW_MASK_PSTATE

#undef PSW_MASK_ASC

#undef PSW_SHIFT_ASC

#undef PSW_MASK_CC

#undef PSW_MASK_PM

#undef PSW_MASK_64
@@ -315,11 +316,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); 
#define PSW_MASK_IO             0x0200000000000000ULL

#define PSW_MASK_EXT            0x0100000000000000ULL

#define PSW_MASK_KEY            0x00F0000000000000ULL

#define PSW_SHIFT_KEY           56

#define PSW_SHIFT_KEY           52

#define PSW_MASK_MCHECK         0x0004000000000000ULL

#define PSW_MASK_WAIT           0x0002000000000000ULL

#define PSW_MASK_PSTATE         0x0001000000000000ULL

#define PSW_MASK_ASC            0x0000C00000000000ULL

#define PSW_SHIFT_ASC           46

#define PSW_MASK_CC             0x0000300000000000ULL

#define PSW_MASK_PM             0x00000F0000000000ULL

#define PSW_MASK_64             0x0000000100000000ULL
@@ -336,24 +338,26 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); 
#define PSW_ASC_SECONDARY       0x0000800000000000ULL

#define PSW_ASC_HOME            0x0000C00000000000ULL



/* the address space values shifted */

#define AS_PRIMARY              0

#define AS_ACCREG               1

#define AS_SECONDARY            2

#define AS_HOME                 3



/* tb flags */



#define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)

#define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)

#define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)

#define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)

#define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)

#define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)

#define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)

#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)

#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)

#define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)

#define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)

#define FLAG_MASK_64            (PSW_MASK_64     >> 32)

#define FLAG_MASK_32            0x00001000

#define FLAG_MASK_PSW_SHIFT     31

#define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_PSW		(FLAG_MASK_PER | FLAG_MASK_PSTATE \

                                | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)



/* Control register 0 bits */

#define CR0_LOWPROT             0x0000000010000000ULL

#define CR0_SECONDARY           0x0000000004000000ULL

#define CR0_EDAT                0x0000000000800000ULL



/* MMU */
@@ -361,6 +365,17 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); 
#define MMU_SECONDARY_IDX       1

#define MMU_HOME_IDX            2



static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)

{

    uint16_t pkm = env->cregs[3] >> 16;



    if (env->psw.mask & PSW_MASK_PSTATE) {

        /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */

        return pkm & (0x80 >> psw_key);

    }

    return true;

}



static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)

{

    switch (env->psw.mask & PSW_MASK_ASC) {
@@ -396,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 
{

    *pc = env->psw.addr;

    *cs_base = env->ex_value;

    *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |

             ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);

    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;

}



#define MAX_ILEN 6

target/s390x/cpu_models.c

+6 −0
Original line number Diff line number Diff line
@@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel *max_model, 
static void add_qemu_cpu_model_features(S390FeatBitmap fbm)

{

    static const int feats[] = {

        S390_FEAT_DAT_ENH,

        S390_FEAT_STFLE,

        S390_FEAT_EXTENDED_IMMEDIATE,

        S390_FEAT_EXTENDED_TRANSLATION_2,
@@ -682,9 +683,14 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm) 
        S390_FEAT_LONG_DISPLACEMENT_FAST,

        S390_FEAT_ETF2_ENH,

        S390_FEAT_STORE_CLOCK_FAST,

        S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,

        S390_FEAT_GENERAL_INSTRUCTIONS_EXT,

        S390_FEAT_EXECUTE_EXT,

        S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,

        S390_FEAT_STFLE_45,

        S390_FEAT_STFLE_49,

        S390_FEAT_LOCAL_TLB_CLEARING,

        S390_FEAT_STFLE_53,

    };

    int i;

target/s390x/helper.h

+2 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) 
DEF_HELPER_2(stfle, i32, env, i64)

DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)

DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)

DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)
@@ -130,6 +131,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) 
DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)

DEF_HELPER_4(sigp, i32, env, i64, i32, i64)

DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64)

DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)

DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)

DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env)

DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env)

target/s390x/insn-data.def

+30 −0
Original line number Diff line number Diff line
@@ -134,6 +134,15 @@ 
    D(0x8500, BRXLE,   RSI,   Z,   0, 0, 0, 0, bx32, 0, 1)

    D(0xec44, BRXHG,   RIE_e, Z,   0, 0, 0, 0, bx64, 0, 0)

    D(0xec45, BRXHLE,  RIE_e, Z,   0, 0, 0, 0, bx64, 0, 1)

/* BRANCH PREDICTION PRELOAD */

    /* ??? Format is SMI, but implemented as NOP, so we need no fields.  */

    C(0xc700, BPP,     E,     EH,  0, 0, 0, 0, 0, 0)

/* BRANCH PREDICTION RELATIVE PRELOAD */

    /* ??? Format is MII, but implemented as NOP, so we need no fields.  */

    C(0xc500, BPRP,    E,     EH,  0, 0, 0, 0, 0, 0)

/* NEXT INSTRUCTION ACCESS INTENT */

    /* ??? Format is IE, but implemented as NOP, so we need no fields.  */

    C(0xb2fa, NIAI,    E,     EH,  0, 0, 0, 0, 0, 0)



/* CHECKSUM */

    C(0xb241, CKSM,    RRE,   Z,   r1_o, ra2, new, r1_32, cksm, 0)
@@ -427,6 +436,11 @@ 
/* LOAD AND TRAP */

    C(0xe39f, LAT,     RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)

    C(0xe385, LGAT,    RXY_a, LAT, 0, a2, r1, 0, lgat, 0)

/* LOAD AND ZERO RIGHTMOST BYTE */

    C(0xe3eb, LZRF,    RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)

    C(0xe32a, LZRG,    RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)

/* LOAD LOGICAL AND ZERO RIGHTMOST BYTE */

    C(0xe33a, LLZRGF,  RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)

/* LOAD BYTE */

    C(0xb926, LBR,     RRE,   EI,  0, r2_8s, 0, r1_32, mov2, 0)

    C(0xb906, LGBR,    RRE,   EI,  0, r2_8s, 0, r1, mov2, 0)
@@ -514,6 +528,13 @@ 
    C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)

    C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)

    C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)

/* LOAD HALFWORD IMMEDIATE ON CONDITION */

    C(0xec42, LOCHI,   RIE_g, LOC2, r1, i2, new, r1_32, loc, 0)

    C(0xec46, LOCGHI,  RIE_g, LOC2, r1, i2, r1, 0, loc, 0)

    C(0xec4e, LOCHHI,  RIE_g, LOC2, r1_sr32, i2, new, r1_32h, loc, 0)

/* LOAD HIGH ON CONDITION */

    C(0xb9e0, LOCFHR,  RRF_c, LOC2, r1_sr32, r2, new, r1_32h, loc, 0)

    C(0xebe0, LOCFH,   RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0)

/* LOAD PAIR DISJOINT */

    D(0xc804, LPD,     SSF,   ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)

    D(0xc805, LPDG,    SSF,   ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ)
@@ -590,6 +611,8 @@ 
    C(0xb254, MVPG,    RRE,   Z,   r1_o, r2_o, 0, 0, mvpg, 0)

/* MOVE STRING */

    C(0xb255, MVST,    RRE,   Z,   r1_o, r2_o, 0, 0, mvst, 0)

/* MOVE WITH OPTIONAL SPECIFICATION */

    C(0xc800, MVCOS,   SSF,   MVCOS, la1, a2, 0, 0, mvcos, 0)

/* MOVE WITH OFFSET */

    /* Really format SS_b, but we pack both lengths into one argument

       for the helper call, so we might as well leave one 8-bit field.  */
@@ -676,6 +699,9 @@ 
    /* Implemented as nops of course.  */

    C(0xe336, PFD,     RXY_b, GIE, 0, 0, 0, 0, 0, 0)

    C(0xc602, PFDRL,   RIL_c, GIE, 0, 0, 0, 0, 0, 0)

/* PERFORM PROCESSOR ASSIST */

    /* Implemented as nop of course.  */

    C(0xb2e8, PPA,     RRF_c, PPA, 0, 0, 0, 0, 0, 0)



/* POPULATION COUNT */

    C(0xb9e1, POPCNT,  RRE,   PC,  0, r2_o, r1, 0, popcnt, nz64)
@@ -777,6 +803,8 @@ 
/* STORE ON CONDITION */

    D(0xebf3, STOC,    RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)

    D(0xebe3, STOCG,   RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)

/* STORE HIGH ON CONDITION */

    D(0xebe1, STOCFH,  RSY_b, LOC2, 0, 0, 0, 0, soc, 0, 2)

/* STORE REVERSED */

    C(0xe33f, STRVH,   RXY_a, Z,   la2, r1_16u, new, m1_16, rev16, 0)

    C(0xe33e, STRV,    RXY_a, Z,   la2, r1_32u, new, m1_32, rev32, 0)
@@ -900,6 +928,8 @@ 
    C(0x8300, DIAG,    RSI,   Z,   0, 0, 0, 0, diag, 0)

/* INSERT STORAGE KEY EXTENDED */

    C(0xb229, ISKE,    RRE,   Z,   0, r2_o, new, r1_8, iske, 0)

/* INVALIDATE DAT TABLE ENTRY */

    C(0xb98e, IPDE,    RRF_b, Z,   r1_o, r2_o, 0, 0, idte, 0)

/* INVALIDATE PAGE TABLE ENTRY */

    C(0xb221, IPTE,    RRF_a, Z,   r1_o, r2_o, 0, 0, ipte, 0)

/* LOAD CONTROL */

target/s390x/insn-format.def

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16)) 
F3(RIE_d, R(1, 8),     I(2,16,16),  R(3,12))

F3(RIE_e, R(1, 8),     I(2,16,16),  R(3,12))

F5(RIE_f, R(1, 8),     R(2,12),     I(3,16,8), I(4,24,8),  I(5,32,8))

F3(RIE_g, R(1, 8),     I(2,16,16),  M(3,12))

F2(RIL_a, R(1, 8),     I(2,16,32))

F2(RIL_b, R(1, 8),     I(2,16,32))

F2(RIL_c, M(1, 8),     I(2,16,32))