Commit 9263dec8 authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191119' into staging 



target-arm queue:
 * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
 * Relax r13 restriction for ldrex/strex for v8.0
 * Do not reject rt == rt2 for strexd
 * net/cadence_gem: Set PHY autonegotiation restart status
 * ssi: xilinx_spips: Skip spi bus update for a few register writes
 * pl031: Expose RTCICR as proper WC register

# gpg: Signature made Tue 19 Nov 2019 13:30:35 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191119:
  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
  target/arm: Relax r13 restriction for ldrex/strex for v8.0
  target/arm: Do not reject rt == rt2 for strexd
  net/cadence_gem: Set PHY autonegotiation restart status
  ssi: xilinx_spips: Skip spi bus update for a few register writes
  target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
  pl031: Expose RTCICR as proper WC register

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 6e5d4999 04c9c81b

hw/net/cadence_gem.c

+5 −4
Original line number Diff line number Diff line
@@ -274,6 +274,7 @@ 
#define PHY_REG_CONTROL_RST       0x8000

#define PHY_REG_CONTROL_LOOP      0x4000

#define PHY_REG_CONTROL_ANEG      0x1000

#define PHY_REG_CONTROL_ANRESTART 0x0200



#define PHY_REG_STATUS_LINK     0x0004

#define PHY_REG_STATUS_ANEGCMPL 0x0020
@@ -1345,7 +1346,7 @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 
        }

        if (val & PHY_REG_CONTROL_ANEG) {

            /* Complete autonegotiation immediately */

            val &= ~PHY_REG_CONTROL_ANEG;

            val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);

            s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;

        }

        if (val & PHY_REG_CONTROL_LOOP) {

hw/rtc/pl031.c

+1 −5
Original line number Diff line number Diff line
@@ -149,11 +149,7 @@ static void pl031_write(void * opaque, hwaddr offset, 
        pl031_update(s);

        break;

    case RTC_ICR:

        /* The PL031 documentation (DDI0224B) states that the interrupt is

           cleared when bit 0 of the written value is set.  However the

           arm926e documentation (DDI0287B) states that the interrupt is

           cleared when any value is written.  */

        s->is = 0;

        s->is &= ~value;

        pl031_update(s);

        break;

    case RTC_CR:

hw/ssi/xilinx_spips.c

+18 −4
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
#define R_GPIO              (0x30 / 4)

#define R_LPBK_DLY_ADJ      (0x38 / 4)

#define R_LPBK_DLY_ADJ_RESET (0x33)

#define R_IOU_TAPDLY_BYPASS (0x3C / 4)

#define R_TXD1              (0x80 / 4)

#define R_TXD2              (0x84 / 4)

#define R_TXD3              (0x88 / 4)
@@ -139,6 +140,8 @@ 
#define R_LQSPI_STS         (0xA4 / 4)

#define LQSPI_STS_WR_RECVD      (1 << 1)



#define R_DUMMY_CYCLE_EN    (0xC8 / 4)

#define R_ECO               (0xF8 / 4)

#define R_MOD_ID            (0xFC / 4)



#define R_GQSPI_SELECT          (0x144 / 4)
@@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, 
{

    int mask = ~0;

    XilinxSPIPS *s = opaque;

    bool try_flush = true;



    DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);

    addr >>= 2;
@@ -1019,14 +1023,24 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, 
        tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,

                      s->regs[R_CONFIG] & R_CONFIG_ENDIAN);

        goto no_reg_update;

    /* Skip SPI bus update for below registers writes */

    case R_GPIO:

    case R_LPBK_DLY_ADJ:

    case R_IOU_TAPDLY_BYPASS:

    case R_DUMMY_CYCLE_EN:

    case R_ECO:

        try_flush = false;

        break;

    }

    s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);

no_reg_update:

    if (try_flush) {

        xilinx_spips_update_cs_lines(s);

        xilinx_spips_check_flush(s);

        xilinx_spips_update_cs_lines(s);

        xilinx_spips_update_ixr(s);

    }

}



static const MemoryRegionOps spips_ops = {

    .read = xilinx_spips_read,

target/arm/cpu.h

+2 −3
Original line number Diff line number Diff line
@@ -185,12 +185,9 @@ typedef struct { 
#ifdef TARGET_AARCH64

# define ARM_MAX_VQ    16

void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);

uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);

#else

# define ARM_MAX_VQ    1

static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }

static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)

{ return 0; }

#endif



typedef struct ARMVectorReg {
@@ -1317,6 +1314,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 
    if (mask & XPSR_GE) {

        env->GE = (val & XPSR_GE) >> 16;

    }

#ifndef CONFIG_USER_ONLY

    if (mask & XPSR_T) {

        env->thumb = ((val & XPSR_T) != 0);

    }
@@ -1332,6 +1330,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 
        /* Note that this only happens on exception exit */

        write_v7m_exception(env, val & XPSR_EXCP);

    }

#endif

}



#define HCR_VM        (1ULL << 0)

target/arm/cpu64.c

+0 −15
Original line number Diff line number Diff line
@@ -458,21 +458,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) 
    cpu->sve_max_vq = max_vq;

}



uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)

{

    uint32_t bitnum;



    /*

     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want

     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this

     * function always returns the next smaller than the input.

     */

    assert(vq && vq <= ARM_MAX_VQ + 1);



    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);

    return bitnum == vq - 1 ? 0 : bitnum + 1;

}



static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,

                                   void *opaque, Error **errp)

{