Commit 91d35509 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160706' into staging 



misc updates

# gpg: Signature made Wed 06 Jul 2016 17:17:02 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-tcg-20160706:
  tcg: Improve the alignment check infrastructure
  tcg: Optimize spills of constants
  tcg: Fix name for high-half register
  build: Use $(CCAS) for compiling .S files

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0c56c6ab 1f00b27f

configure

+10 −3
Original line number Diff line number Diff line
@@ -368,7 +368,7 @@ else 
fi



ar="${AR-${cross_prefix}ar}"

as="${AS-${cross_prefix}as}"

ccas="${CCAS-$cc}"

cpp="${CPP-$cc -E}"

objcopy="${OBJCOPY-${cross_prefix}objcopy}"

ld="${LD-${cross_prefix}ld}"
@@ -4490,6 +4490,13 @@ if test "$fortify_source" != "no"; then 
  fi

fi



#################################################

# clang does not support the 16-bit assembly for roms



if echo | $ccas -dM -E - | grep __clang__ > /dev/null 2>&1 ; then

  ccas="$ccas -fno-integrated-as"

fi



##########################################

# check if struct fsxattr is available via linux/fs.h
@@ -5508,7 +5515,7 @@ echo "CXX=$cxx" >> $config_host_mak 
echo "OBJCC=$objcc" >> $config_host_mak

echo "AR=$ar" >> $config_host_mak

echo "ARFLAGS=$ARFLAGS" >> $config_host_mak

echo "AS=$as" >> $config_host_mak

echo "CCAS=$ccas" >> $config_host_mak

echo "CPP=$cpp" >> $config_host_mak

echo "OBJCOPY=$objcopy" >> $config_host_mak

echo "LD=$ld" >> $config_host_mak
@@ -5981,7 +5988,7 @@ for rom in seabios vgabios ; do 
    config_mak=roms/$rom/config.mak

    echo "# Automatically generated by configure - do not modify" > $config_mak

    echo "SRC_PATH=$source_path/roms/$rom" >> $config_mak

    echo "AS=$as" >> $config_mak

    echo "CCAS=$ccas" >> $config_mak

    echo "CC=$cc" >> $config_mak

    echo "BCC=bcc" >> $config_mak

    echo "CPP=$cpp" >> $config_mak

include/exec/cpu-all.h

+12 −4
Original line number Diff line number Diff line
@@ -288,14 +288,22 @@ CPUArchState *cpu_copy(CPUArchState *env); 
#if !defined(CONFIG_USER_ONLY)



/* Flags stored in the low bits of the TLB virtual address.  These are

   defined so that fast path ram access is all zeros.  */

 * defined so that fast path ram access is all zeros.

 * The flags all must be between TARGET_PAGE_BITS and

 * maximum address alignment bit.

 */

/* Zero if TLB entry is valid.  */

#define TLB_INVALID_MASK   (1 << 3)

#define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS - 1))

/* Set if TLB entry references a clean RAM page.  The iotlb entry will

   contain the page physical address.  */

#define TLB_NOTDIRTY    (1 << 4)

#define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS - 2))

/* Set if TLB entry is an IO callback.  */

#define TLB_MMIO        (1 << 5)

#define TLB_MMIO            (1 << (TARGET_PAGE_BITS - 3))



/* Use this mask to check interception with an alignment mask

 * in a TCG backend.

 */

#define TLB_FLAGS_MASK  (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO)



void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);

void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);

rules.mak

+2 −5
Original line number Diff line number Diff line
@@ -68,11 +68,8 @@ LINK = $(call quiet-command, $(LINKPROG) $(QEMU_CFLAGS) $(CFLAGS) $(LDFLAGS) -o 
       $(call process-archive-undefs, $1) \

       $(version-obj-y) $(call extract-libs,$1) $(LIBS),"  LINK  $(TARGET_DIR)$@")



%.asm: %.S

	$(call quiet-command,$(CPP) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) -o $@ $<,"  CPP   $(TARGET_DIR)$@")



%.o: %.asm

	$(call quiet-command,$(AS) $(ASFLAGS) -o $@ $<,"  AS    $(TARGET_DIR)$@")

%.o: %.S

	$(call quiet-command,$(CCAS) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) -c -o $@ $<,"  AS    $(TARGET_DIR)$@")



%.o: %.cc

	$(call quiet-command,$(CXX) $(QEMU_INCLUDES) $(QEMU_CXXFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) -c -o $@ $<,"  CXX   $(TARGET_DIR)$@")

softmmu_template.h

+24 −64
Original line number Diff line number Diff line
@@ -171,20 +171,21 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
    unsigned mmu_idx = get_mmuidx(oi);

    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;

    int a_bits = get_alignment_bits(get_memop(oi));

    uintptr_t haddr;

    DATA_TYPE res;



    /* Adjust the given return address.  */

    retaddr -= GETPC_ADJ;



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if ((addr & (DATA_SIZE - 1)) != 0

            && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

    if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                             mmu_idx, retaddr);

    }



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);
@@ -215,10 +216,6 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
        DATA_TYPE res1, res2;

        unsigned shift;

    do_unaligned_access:

        if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {

            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                                 mmu_idx, retaddr);

        }

        addr1 = addr & ~(DATA_SIZE - 1);

        addr2 = addr1 + DATA_SIZE;

        /* Note the adjustment at the beginning of the function.
@@ -232,13 +229,6 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
        return res;

    }



    /* Handle aligned access or unaligned access in the same page.  */

    if ((addr & (DATA_SIZE - 1)) != 0

        && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                             mmu_idx, retaddr);

    }



    haddr = addr + env->tlb_table[mmu_idx][index].addend;

#if DATA_SIZE == 1

    res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
@@ -255,20 +245,21 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
    unsigned mmu_idx = get_mmuidx(oi);

    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;

    int a_bits = get_alignment_bits(get_memop(oi));

    uintptr_t haddr;

    DATA_TYPE res;



    /* Adjust the given return address.  */

    retaddr -= GETPC_ADJ;



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if ((addr & (DATA_SIZE - 1)) != 0

            && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

    if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                             mmu_idx, retaddr);

    }



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);
@@ -299,10 +290,6 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
        DATA_TYPE res1, res2;

        unsigned shift;

    do_unaligned_access:

        if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {

            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                                 mmu_idx, retaddr);

        }

        addr1 = addr & ~(DATA_SIZE - 1);

        addr2 = addr1 + DATA_SIZE;

        /* Note the adjustment at the beginning of the function.
@@ -316,13 +303,6 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
        return res;

    }



    /* Handle aligned access or unaligned access in the same page.  */

    if ((addr & (DATA_SIZE - 1)) != 0

        && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

                             mmu_idx, retaddr);

    }



    haddr = addr + env->tlb_table[mmu_idx][index].addend;

    res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);

    return res;
@@ -376,19 +356,20 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    unsigned mmu_idx = get_mmuidx(oi);

    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;

    int a_bits = get_alignment_bits(get_memop(oi));

    uintptr_t haddr;



    /* Adjust the given return address.  */

    retaddr -= GETPC_ADJ;



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if ((addr & (DATA_SIZE - 1)) != 0

            && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

    if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                             mmu_idx, retaddr);

    }



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

        }
@@ -416,10 +397,6 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
                     >= TARGET_PAGE_SIZE)) {

        int i;

    do_unaligned_access:

        if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {

            cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                                 mmu_idx, retaddr);

        }

        /* XXX: not efficient, but simple */

        /* Note: relies on the fact that tlb_fill() does not remove the

         * previous page from the TLB cache.  */
@@ -434,13 +411,6 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        return;

    }



    /* Handle aligned access or unaligned access in the same page.  */

    if ((addr & (DATA_SIZE - 1)) != 0

        && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                             mmu_idx, retaddr);

    }



    haddr = addr + env->tlb_table[mmu_idx][index].addend;

#if DATA_SIZE == 1

    glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
@@ -456,19 +426,20 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    unsigned mmu_idx = get_mmuidx(oi);

    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;

    int a_bits = get_alignment_bits(get_memop(oi));

    uintptr_t haddr;



    /* Adjust the given return address.  */

    retaddr -= GETPC_ADJ;



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if ((addr & (DATA_SIZE - 1)) != 0

            && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

    if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                             mmu_idx, retaddr);

    }



    /* If the TLB entry is for a different page, reload and try again.  */

    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

        }
@@ -496,10 +467,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
                     >= TARGET_PAGE_SIZE)) {

        int i;

    do_unaligned_access:

        if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {

            cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                                 mmu_idx, retaddr);

        }

        /* XXX: not efficient, but simple */

        /* Note: relies on the fact that tlb_fill() does not remove the

         * previous page from the TLB cache.  */
@@ -514,13 +481,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        return;

    }



    /* Handle aligned access or unaligned access in the same page.  */

    if ((addr & (DATA_SIZE - 1)) != 0

        && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {

        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,

                             mmu_idx, retaddr);

    }



    haddr = addr + env->tlb_table[mmu_idx][index].addend;

    glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);

}

tcg/aarch64/tcg-target.inc.c

+15 −4
Original line number Diff line number Diff line
@@ -716,6 +716,16 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 
                 arg, arg1, arg2);

}



static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,

                               TCGReg base, intptr_t ofs)

{

    if (val == 0) {

        tcg_out_st(s, type, TCG_REG_XZR, base, ofs);

        return true;

    }

    return false;

}



static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,

                               TCGReg rn, unsigned int a, unsigned int b)

{
@@ -1071,19 +1081,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, 
    int tlb_offset = is_read ?

        offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)

        : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);

    int s_mask = (1 << (opc & MO_SIZE)) - 1;

    int a_bits = get_alignment_bits(opc);

    TCGReg base = TCG_AREG0, x3;

    uint64_t tlb_mask;



    /* For aligned accesses, we check the first byte and include the alignment

       bits within the address.  For unaligned access, we check that we don't

       cross pages using the address of the last byte of the access.  */

    if ((opc & MO_AMASK) == MO_ALIGN || s_mask == 0) {

        tlb_mask = TARGET_PAGE_MASK | s_mask;

    if (a_bits >= 0) {

        /* A byte access or an alignment check required */

        tlb_mask = TARGET_PAGE_MASK | ((1 << a_bits) - 1);

        x3 = addr_reg;

    } else {

        tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64,

                     TCG_REG_X3, addr_reg, s_mask);

                     TCG_REG_X3, addr_reg, (1 << (opc & MO_SIZE)) - 1);

        tlb_mask = TARGET_PAGE_MASK;

        x3 = TCG_REG_X3;

    }