Commit 9196dd41 authored by Blue Swirl's avatar Blue Swirl
Browse files

Merge branch 'arm-devs.next' of git://git.linaro.org/people/pmaydell/qemu-arm 

* 'arm-devs.next' of git://git.linaro.org/people/pmaydell/qemu-arm:
  hw/nand.c: Fix nand erase operation
  cadence_uart: Flush queued characters on reset
  pl330: Don't inhibit ES bits on INTEN
  pflash_cfi01: Implement migration support
  pflash_cfi01: Drop unused 'bypass' field
  hw/arm_gic_common: Use vmstate struct rather than save/load functions
  arm_gic: Fix sizes of state fields in preparation for vmstate support
  vmstate: Add support for two dimensional arrays
  hw/onenand.c: fix migration of dynamically allocated buffer "otp"
  hw/sd.c: fix migration of dynamically allocated buffer "buf"
  vmstate.h: introduce VMSTATE_BUFFER_POINTER_UNSAFE macro
  hw/arm_mptimer: Save the timer state
  pl050: Don't send always-constant is_mouse field
  hw/arm/nseries: don't print to stdout or stderr
parents 893986fe 32aea752

hw/arm/nseries.c

+5 −13
Original line number Diff line number Diff line
@@ -129,8 +129,6 @@ static void n800_mmc_cs_cb(void *opaque, int line, int level) 
    /* TODO: this seems to actually be connected to the menelaus, to

     * which also both MMC slots connect.  */

    omap_mmc_enable((struct omap_mmc_s *) opaque, !level);



    printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);

}



static void n8x0_gpio_setup(struct n800_s *s)
@@ -428,9 +426,6 @@ struct mipid_s { 


static void mipid_reset(struct mipid_s *s)

{

    if (!s->sleep)

        fprintf(stderr, "%s: Display off\n", __FUNCTION__);



    s->pm = 0;

    s->cmd = 0;
@@ -578,11 +573,9 @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) 


    case 0x28:	/* DISPOFF */

        s->onoff = 0;

        fprintf(stderr, "%s: Display off\n", __FUNCTION__);

        break;

    case 0x29:	/* DISPON */

        s->onoff = 1;

        fprintf(stderr, "%s: Display on\n", __FUNCTION__);

        break;



    case 0x2a:	/* CASET */
@@ -669,7 +662,8 @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) 


    default:

    bad_cmd:

        fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: unknown command %02x\n", __func__, s->cmd);

        break;

    }
@@ -1347,7 +1341,6 @@ static void n8x0_init(QEMUMachineInitArgs *args, 


    if (option_rom[0].name &&

        (args->boot_device[0] == 'n' || !args->kernel_filename)) {

        int rom_size;

        uint8_t nolo_tags[0x10000];

        /* No, wait, better start at the ROM.  */

        s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
@@ -1361,10 +1354,9 @@ static void n8x0_init(QEMUMachineInitArgs *args, 
         *

         * The code above is for loading the `zImage' file from Nokia

         * images.  */

        rom_size = load_image_targphys(option_rom[0].name,

        load_image_targphys(option_rom[0].name,

                            OMAP2_Q2_BASE + 0x400000,

                            sdram_size - 0x400000);

        printf("%i bytes of image loaded\n", rom_size);



        n800_setup_nolo_tags(nolo_tags);

        cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);

hw/arm_gic_common.c

+43 −69
Original line number Diff line number Diff line
@@ -20,89 +20,64 @@ 


#include "hw/arm_gic_internal.h"



static void gic_save(QEMUFile *f, void *opaque)

static void gic_pre_save(void *opaque)

{

    GICState *s = (GICState *)opaque;

    ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);

    int i;

    int j;



    if (c->pre_save) {

        c->pre_save(s);

    }



    qemu_put_be32(f, s->enabled);

    for (i = 0; i < s->num_cpu; i++) {

        qemu_put_be32(f, s->cpu_enabled[i]);

        for (j = 0; j < GIC_INTERNAL; j++) {

            qemu_put_be32(f, s->priority1[j][i]);

        }

        for (j = 0; j < s->num_irq; j++) {

            qemu_put_be32(f, s->last_active[j][i]);

        }

        qemu_put_be32(f, s->priority_mask[i]);

        qemu_put_be32(f, s->running_irq[i]);

        qemu_put_be32(f, s->running_priority[i]);

        qemu_put_be32(f, s->current_pending[i]);

    }

    for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {

        qemu_put_be32(f, s->priority2[i]);

    }

    for (i = 0; i < s->num_irq; i++) {

        qemu_put_be32(f, s->irq_target[i]);

        qemu_put_byte(f, s->irq_state[i].enabled);

        qemu_put_byte(f, s->irq_state[i].pending);

        qemu_put_byte(f, s->irq_state[i].active);

        qemu_put_byte(f, s->irq_state[i].level);

        qemu_put_byte(f, s->irq_state[i].model);

        qemu_put_byte(f, s->irq_state[i].trigger);

    }

}



static int gic_load(QEMUFile *f, void *opaque, int version_id)

static int gic_post_load(void *opaque, int version_id)

{

    GICState *s = (GICState *)opaque;

    ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);

    int i;

    int j;



    if (version_id != 3) {

        return -EINVAL;

    }



    s->enabled = qemu_get_be32(f);

    for (i = 0; i < s->num_cpu; i++) {

        s->cpu_enabled[i] = qemu_get_be32(f);

        for (j = 0; j < GIC_INTERNAL; j++) {

            s->priority1[j][i] = qemu_get_be32(f);

        }

        for (j = 0; j < s->num_irq; j++) {

            s->last_active[j][i] = qemu_get_be32(f);

        }

        s->priority_mask[i] = qemu_get_be32(f);

        s->running_irq[i] = qemu_get_be32(f);

        s->running_priority[i] = qemu_get_be32(f);

        s->current_pending[i] = qemu_get_be32(f);

    }

    for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {

        s->priority2[i] = qemu_get_be32(f);

    if (c->post_load) {

        c->post_load(s);

    }

    for (i = 0; i < s->num_irq; i++) {

        s->irq_target[i] = qemu_get_be32(f);

        s->irq_state[i].enabled = qemu_get_byte(f);

        s->irq_state[i].pending = qemu_get_byte(f);

        s->irq_state[i].active = qemu_get_byte(f);

        s->irq_state[i].level = qemu_get_byte(f);

        s->irq_state[i].model = qemu_get_byte(f);

        s->irq_state[i].trigger = qemu_get_byte(f);

    return 0;

}



    if (c->post_load) {

        c->post_load(s);

static const VMStateDescription vmstate_gic_irq_state = {

    .name = "arm_gic_irq_state",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT8(enabled, gic_irq_state),

        VMSTATE_UINT8(pending, gic_irq_state),

        VMSTATE_UINT8(active, gic_irq_state),

        VMSTATE_UINT8(level, gic_irq_state),

        VMSTATE_BOOL(model, gic_irq_state),

        VMSTATE_BOOL(trigger, gic_irq_state),

        VMSTATE_END_OF_LIST()

    }

};



    return 0;

static const VMStateDescription vmstate_gic = {

    .name = "arm_gic",

    .version_id = 4,

    .minimum_version_id = 4,

    .pre_save = gic_pre_save,

    .post_load = gic_post_load,

    .fields = (VMStateField[]) {

        VMSTATE_BOOL(enabled, GICState),

        VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, NCPU),

        VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,

                             vmstate_gic_irq_state, gic_irq_state),

        VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),

        VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, NCPU),

        VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),

        VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, NCPU),

        VMSTATE_UINT16_ARRAY(priority_mask, GICState, NCPU),

        VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU),

        VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU),

        VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU),

        VMSTATE_END_OF_LIST()

    }

};



static void arm_gic_common_realize(DeviceState *dev, Error **errp)

{
@@ -131,8 +106,6 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp) 
                   num_irq);

        return;

    }



    register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);

}



static void arm_gic_common_reset(DeviceState *dev)
@@ -149,7 +122,7 @@ static void arm_gic_common_reset(DeviceState *dev) 
        s->current_pending[i] = 1023;

        s->running_irq[i] = 1023;

        s->running_priority[i] = 0x100;

        s->cpu_enabled[i] = 0;

        s->cpu_enabled[i] = false;

    }

    for (i = 0; i < 16; i++) {

        GIC_SET_ENABLED(i, ALL_CPU_MASK);
@@ -161,7 +134,7 @@ static void arm_gic_common_reset(DeviceState *dev) 
            s->irq_target[i] = 1;

        }

    }

    s->enabled = 0;

    s->enabled = false;

}



static Property arm_gic_common_properties[] = {
@@ -182,6 +155,7 @@ static void arm_gic_common_class_init(ObjectClass *klass, void *data) 
    dc->reset = arm_gic_common_reset;

    dc->realize = arm_gic_common_realize;

    dc->props = arm_gic_common_properties;

    dc->vmsd = &vmstate_gic;

    dc->no_user = 1;

}

hw/arm_gic_internal.h

+21 −21
Original line number Diff line number Diff line
@@ -45,14 +45,14 @@ 
#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)

#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)

#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)

#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1

#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0

#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true

#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false

#define GIC_TEST_MODEL(irq) s->irq_state[irq].model

#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)

#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)

#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)

#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1

#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0

#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true

#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false

#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger

#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ?            \

                                    s->priority1[irq][cpu] :            \
@@ -61,30 +61,30 @@ 


typedef struct gic_irq_state {

    /* The enable bits are only banked for per-cpu interrupts.  */

    unsigned enabled:NCPU;

    unsigned pending:NCPU;

    unsigned active:NCPU;

    unsigned level:NCPU;

    unsigned model:1; /* 0 = N:N, 1 = 1:N */

    unsigned trigger:1; /* nonzero = edge triggered.  */

    uint8_t enabled;

    uint8_t pending;

    uint8_t active;

    uint8_t level;

    bool model; /* 0 = N:N, 1 = 1:N */

    bool trigger; /* nonzero = edge triggered.  */

} gic_irq_state;



typedef struct GICState {

    SysBusDevice busdev;

    qemu_irq parent_irq[NCPU];

    int enabled;

    int cpu_enabled[NCPU];

    bool enabled;

    bool cpu_enabled[NCPU];



    gic_irq_state irq_state[GIC_MAXIRQ];

    int irq_target[GIC_MAXIRQ];

    int priority1[GIC_INTERNAL][NCPU];

    int priority2[GIC_MAXIRQ - GIC_INTERNAL];

    int last_active[GIC_MAXIRQ][NCPU];



    int priority_mask[NCPU];

    int running_irq[NCPU];

    int running_priority[NCPU];

    int current_pending[NCPU];

    uint8_t irq_target[GIC_MAXIRQ];

    uint8_t priority1[GIC_INTERNAL][NCPU];

    uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];

    uint16_t last_active[GIC_MAXIRQ][NCPU];



    uint16_t priority_mask[NCPU];

    uint16_t running_irq[NCPU];

    uint16_t running_priority[NCPU];

    uint16_t current_pending[NCPU];



    uint32_t num_cpu;

hw/arm_mptimer.c

+3 −2
Original line number Diff line number Diff line
@@ -253,14 +253,15 @@ static int arm_mptimer_init(SysBusDevice *dev) 


static const VMStateDescription vmstate_timerblock = {

    .name = "arm_mptimer_timerblock",

    .version_id = 1,

    .minimum_version_id = 1,

    .version_id = 2,

    .minimum_version_id = 2,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(count, TimerBlock),

        VMSTATE_UINT32(load, TimerBlock),

        VMSTATE_UINT32(control, TimerBlock),

        VMSTATE_UINT32(status, TimerBlock),

        VMSTATE_INT64(tick, TimerBlock),

        VMSTATE_TIMER(timer, TimerBlock),

        VMSTATE_END_OF_LIST()

    }

};

hw/armv7m_nvic.c

+2 −2
Original line number Diff line number Diff line
@@ -458,10 +458,10 @@ static void armv7m_nvic_reset(DeviceState *dev) 
     * as enabled by default, and with a priority mask which allows

     * all interrupts through.

     */

    s->gic.cpu_enabled[0] = 1;

    s->gic.cpu_enabled[0] = true;

    s->gic.priority_mask[0] = 0x100;

    /* The NVIC as a whole is always enabled. */

    s->gic.enabled = 1;

    s->gic.enabled = true;

    systick_reset(s);

}