Commit 8f6e82e4 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150911' into staging 



queued tcg related patches

# gpg: Signature made Fri 11 Sep 2015 16:17:00 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/pull-tcg-20150911:
  cpu-exec: introduce loop exit with restore function
  softmmu: remove now unused functions
  softmmu: add helper function to pass through retaddr
  tlb: Add "ifetch" argument to cpu_mmu_index()

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 30c38c90 1c3c8af1

cpu-exec.c

+9 −0
Original line number Diff line number Diff line
@@ -134,6 +134,15 @@ void cpu_loop_exit(CPUState *cpu) 
    siglongjmp(cpu->jmp_env, 1);

}



void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)

{

    if (pc) {

        cpu_restore_state(cpu, pc);

    }

    cpu->current_tb = NULL;

    siglongjmp(cpu->jmp_env, 1);

}



/* exit the current TB from a signal handler. The host registers are

   restored in a state compatible with the CPU emulator

 */

cputlb.c

+1 −1
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
    CPUState *cpu = ENV_GET_CPU(env1);



    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = cpu_mmu_index(env1);

    mmu_idx = cpu_mmu_index(env1, true);

    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=

                 (addr & TARGET_PAGE_MASK))) {

        cpu_ldub_code(env1, addr);

include/exec/cpu_ldst.h

+2 −21
Original line number Diff line number Diff line
@@ -113,25 +113,6 @@ 
/* The memory helpers for tcg-generated code need tcg_target_long etc.  */

#include "tcg.h"



uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);



void helper_stb_mmu(CPUArchState *env, target_ulong addr,

                    uint8_t val, int mmu_idx);

void helper_stw_mmu(CPUArchState *env, target_ulong addr,

                    uint16_t val, int mmu_idx);

void helper_stl_mmu(CPUArchState *env, target_ulong addr,

                    uint32_t val, int mmu_idx);

void helper_stq_mmu(CPUArchState *env, target_ulong addr,

                    uint64_t val, int mmu_idx);



uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);



#ifdef MMU_MODE0_SUFFIX

#define CPU_MMU_INDEX 0

#define MEMSUFFIX MMU_MODE0_SUFFIX
@@ -363,7 +344,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 
#endif /* (NB_MMU_MODES > 12) */



/* these access are slower, they must be as rare as possible */

#define CPU_MMU_INDEX (cpu_mmu_index(env))

#define CPU_MMU_INDEX (cpu_mmu_index(env, false))

#define MEMSUFFIX _data

#define DATA_SIZE 1

#include "exec/cpu_ldst_template.h"
@@ -379,7 +360,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 
#undef CPU_MMU_INDEX

#undef MEMSUFFIX



#define CPU_MMU_INDEX (cpu_mmu_index(env))

#define CPU_MMU_INDEX (cpu_mmu_index(env, true))

#define MEMSUFFIX _code

#define SOFTMMU_CODE_ACCESS

include/exec/cpu_ldst_template.h

+51 −8
Original line number Diff line number Diff line
@@ -27,20 +27,24 @@ 
#define SUFFIX q

#define USUFFIX q

#define DATA_TYPE uint64_t

#define SHIFT 3

#elif DATA_SIZE == 4

#define SUFFIX l

#define USUFFIX l

#define DATA_TYPE uint32_t

#define SHIFT 2

#elif DATA_SIZE == 2

#define SUFFIX w

#define USUFFIX uw

#define DATA_TYPE uint16_t

#define DATA_STYPE int16_t

#define SHIFT 1

#elif DATA_SIZE == 1

#define SUFFIX b

#define USUFFIX ub

#define DATA_TYPE uint8_t

#define DATA_STYPE int8_t

#define SHIFT 0

#else

#error unsupported data size

#endif
@@ -54,27 +58,36 @@ 
#ifdef SOFTMMU_CODE_ACCESS

#define ADDR_READ addr_code

#define MMUSUFFIX _cmmu

#define URETSUFFIX SUFFIX

#define SRETSUFFIX SUFFIX

#else

#define ADDR_READ addr_read

#define MMUSUFFIX _mmu

#define URETSUFFIX USUFFIX

#define SRETSUFFIX glue(s, SUFFIX)

#endif



/* generic load/store macros */



static inline RES_TYPE

glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)

glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                  target_ulong ptr,

                                                  uintptr_t retaddr)

{

    int page_index;

    RES_TYPE res;

    target_ulong addr;

    int mmu_idx;

    TCGMemOpIdx oi;



    addr = ptr;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);

        oi = make_memop_idx(SHIFT, mmu_idx);

        res = glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr,

                                                            oi, retaddr);

    } else {

        uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        res = glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr);
@@ -82,27 +95,43 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) 
    return res;

}



static inline RES_TYPE

glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)

{

    return glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);

}



#if DATA_SIZE <= 2

static inline int

glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)

glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                  target_ulong ptr,

                                                  uintptr_t retaddr)

{

    int res, page_index;

    target_ulong addr;

    int mmu_idx;

    TCGMemOpIdx oi;



    addr = ptr;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),

                               MMUSUFFIX)(env, addr, mmu_idx);

        oi = make_memop_idx(SHIFT, mmu_idx);

        res = (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX),

                               MMUSUFFIX)(env, addr, oi, retaddr);

    } else {

        uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        res = glue(glue(lds, SUFFIX), _p)((uint8_t *)hostaddr);

    }

    return res;

}



static inline int

glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)

{

    return glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);

}

#endif



#ifndef SOFTMMU_CODE_ACCESS
@@ -110,25 +139,36 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) 
/* generic store macro */



static inline void

glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,

                                      RES_TYPE v)

glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                 target_ulong ptr,

                                                 RES_TYPE v, uintptr_t retaddr)

{

    int page_index;

    target_ulong addr;

    int mmu_idx;

    TCGMemOpIdx oi;



    addr = ptr;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);

        oi = make_memop_idx(SHIFT, mmu_idx);

        glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi,

                                                     retaddr);

    } else {

        uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        glue(glue(st, SUFFIX), _p)((uint8_t *)hostaddr, v);

    }

}



static inline void

glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,

                                      RES_TYPE v)

{

    glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(env, ptr, v, 0);

}



#endif /* !SOFTMMU_CODE_ACCESS */



#undef RES_TYPE
@@ -139,3 +179,6 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, 
#undef DATA_SIZE

#undef MMUSUFFIX

#undef ADDR_READ

#undef URETSUFFIX

#undef SRETSUFFIX

#undef SHIFT

include/exec/cpu_ldst_useronly_template.h

+25 −0
Original line number Diff line number Diff line
@@ -56,12 +56,28 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) 
    return glue(glue(ld, USUFFIX), _p)(g2h(ptr));

}



static inline RES_TYPE

glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                  target_ulong ptr,

                                                  uintptr_t retaddr)

{

    return glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr);

}



#if DATA_SIZE <= 2

static inline int

glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)

{

    return glue(glue(lds, SUFFIX), _p)(g2h(ptr));

}



static inline int

glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                  target_ulong ptr,

                                                  uintptr_t retaddr)

{

    return glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr);

}

#endif



#ifndef CODE_ACCESS
@@ -71,6 +87,15 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, 
{

    glue(glue(st, SUFFIX), _p)(g2h(ptr), v);

}



static inline void

glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,

                                                  target_ulong ptr,

                                                  RES_TYPE v,

                                                  uintptr_t retaddr)

{

    glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(env, ptr, v);

}

#endif



#undef RES_TYPE