Commit 8f67cd6d authored by Alistair Francis's avatar Alistair Francis
Browse files

riscv: AND stage-1 and stage-2 protection flags 



Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.

Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Tested-by: default avatarAnup Patel <anup@brainfault.org>
Message-id: 846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com
Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com>
parent 38472890

target/riscv/cpu_helper.c

+5 −3
Original line number Diff line number Diff line
@@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
#ifndef CONFIG_USER_ONLY

    vaddr im_address;

    hwaddr pa = 0;

    int prot;

    int prot, prot2;

    bool pmp_violation = false;

    bool m_mode_two_stage = false;

    bool hs_mode_two_stage = false;
@@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
            /* Second stage lookup */

            im_address = pa;



            ret = get_physical_address(env, &pa, &prot, im_address,

            ret = get_physical_address(env, &pa, &prot2, im_address,

                                       access_type, mmu_idx, false, true);



            qemu_log_mask(CPU_LOG_MMU,

                    "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "

                    TARGET_FMT_plx " prot %d\n",

                    __func__, im_address, ret, pa, prot);

                    __func__, im_address, ret, pa, prot2);



            prot &= prot2;



            if (riscv_feature(env, RISCV_FEATURE_PMP) &&

                (ret == TRANSLATE_SUCCESS) &&