Commit 8ec12ec7 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'afaerber/memory-ioport' into staging 



* afaerber/memory-ioport:
  acpi_piix4: Do not use old_portio-style callbacks
  xen_platform: Do not use old_portio-style callbacks
  hw/dma.c: Fix conversion of ioport_register* to MemoryRegion

Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
parents 58a864de c3a29809

hw/acpi_piix4.c

+41 −51
Original line number Diff line number Diff line
@@ -531,68 +531,58 @@ static const MemoryRegionOps piix4_gpe_ops = { 
    .endianness = DEVICE_LITTLE_ENDIAN,

};



static uint32_t pci_up_read(void *opaque, uint32_t addr)

static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)

{

    PIIX4PMState *s = opaque;

    uint32_t val;

    uint32_t val = 0;



    switch (addr) {

    case PCI_UP_BASE - PCI_HOTPLUG_ADDR:

        /* Manufacture an "up" value to cause a device check on any hotplug

         * slot with a device.  Extra device checks are harmless. */

        val = s->pci0_slot_device_present & s->pci0_hotplug_enable;



        PIIX4_DPRINTF("pci_up_read %x\n", val);

    return val;

}



static uint32_t pci_down_read(void *opaque, uint32_t addr)

{

    PIIX4PMState *s = opaque;

    uint32_t val = s->pci0_status.down;



        break;

    case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:

        val = s->pci0_status.down;

        PIIX4_DPRINTF("pci_down_read %x\n", val);

    return val;

}



static uint32_t pci_features_read(void *opaque, uint32_t addr)

{

        break;

    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:

        /* No feature defined yet */

    PIIX4_DPRINTF("pci_features_read %x\n", 0);

    return 0;

        PIIX4_DPRINTF("pci_features_read %x\n", val);

        break;

    case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:

        val = s->pci0_hotplug_enable;

        break;

    default:

        break;

    }



static void pciej_write(void *opaque, uint32_t addr, uint32_t val)

{

    acpi_piix_eject_slot(opaque, val);



    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);

    return val;

}



static uint32_t pcirmv_read(void *opaque, uint32_t addr)

static void pci_write(void *opaque, hwaddr addr, uint64_t data,

                      unsigned int size)

{

    PIIX4PMState *s = opaque;



    return s->pci0_hotplug_enable;

    switch (addr) {

    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:

        acpi_piix_eject_slot(opaque, (uint32_t)data);

        PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n",

                      addr, data);

        break;

    default:

        break;

    }

}



static const MemoryRegionOps piix4_pci_ops = {

    .old_portio = (MemoryRegionPortio[]) {

        {

            .offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR,   .len = 4, .size = 4,

            .read = pci_up_read,

        },{

            .offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,

            .read = pci_down_read,

        },{

            .offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR,   .len = 4, .size = 4,

            .read = pci_features_read,

            .write = pciej_write,

        },{

            .offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR,  .len = 4, .size = 4,

            .read = pcirmv_read,

        },

        PORTIO_END_OF_LIST()

    },

    .read = pci_read,

    .write = pci_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .valid = {

        .min_access_size = 4,

        .max_access_size = 4,

    },

};



static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,

hw/dma.c

+11 −11
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, 


    iport = (nport >> d->dshift) & 0x0f;

    switch (iport) {

    case 0x01:                  /* command */

    case 0x00:                  /* command */

        if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {

            dolog("command %"PRIx64" not supported\n", data);

            return;
@@ -209,7 +209,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, 
        d->command = data;

        break;



    case 0x02:

    case 0x01:

        ichan = data & 3;

        if (data & 4) {

            d->status |= 1 << (ichan + 4);
@@ -221,7 +221,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, 
        DMA_run();

        break;



    case 0x03:                  /* single mask */

    case 0x02:                  /* single mask */

        if (data & 4)

            d->mask |= 1 << (data & 3);

        else
@@ -229,7 +229,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, 
        DMA_run();

        break;



    case 0x04:                  /* mode */

    case 0x03:                  /* mode */

        {

            ichan = data & 3;

#ifdef DEBUG_DMA
@@ -248,23 +248,23 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, 
            break;

        }



    case 0x05:                  /* clear flip flop */

    case 0x04:                  /* clear flip flop */

        d->flip_flop = 0;

        break;



    case 0x06:                  /* reset */

    case 0x05:                  /* reset */

        d->flip_flop = 0;

        d->mask = ~0;

        d->status = 0;

        d->command = 0;

        break;



    case 0x07:                  /* clear mask for all channels */

    case 0x06:                  /* clear mask for all channels */

        d->mask = 0;

        DMA_run();

        break;



    case 0x08:                  /* write mask for all channels */

    case 0x07:                  /* write mask for all channels */

        d->mask = data;

        DMA_run();

        break;
@@ -289,11 +289,11 @@ static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) 


    iport = (nport >> d->dshift) & 0x0f;

    switch (iport) {

    case 0x08:                  /* status */

    case 0x00:                  /* status */

        val = d->status;

        d->status &= 0xf0;

        break;

    case 0x0f:                  /* mask */

    case 0x01:                  /* mask */

        val = d->mask;

        break;

    default:
@@ -468,7 +468,7 @@ void DMA_schedule(int nchan) 
static void dma_reset(void *opaque)

{

    struct dma_cont *d = opaque;

    write_cont(d, (0x06 << d->dshift), 0, 1);

    write_cont(d, (0x05 << d->dshift), 0, 1);

}



static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)

hw/xen_platform.c

+10 −11
Original line number Diff line number Diff line
@@ -279,7 +279,8 @@ static void platform_fixed_ioport_init(PCIXenPlatformState* s) 


/* Xen Platform PCI Device */



static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)

static uint64_t xen_platform_ioport_readb(void *opaque, hwaddr addr,

                                          unsigned int size)

{

    if (addr == 0) {

        return platform_fixed_ioport_readb(opaque, 0);
@@ -288,30 +289,28 @@ static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr) 
    }

}



static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)

static void xen_platform_ioport_writeb(void *opaque, hwaddr addr,

                                       uint64_t val, unsigned int size)

{

    PCIXenPlatformState *s = opaque;



    switch (addr) {

    case 0: /* Platform flags */

        platform_fixed_ioport_writeb(opaque, 0, val);

        platform_fixed_ioport_writeb(opaque, 0, (uint32_t)val);

        break;

    case 8:

        log_writeb(s, val);

        log_writeb(s, (uint32_t)val);

        break;

    default:

        break;

    }

}



static MemoryRegionPortio xen_pci_portio[] = {

    { 0, 0x100, 1, .read = xen_platform_ioport_readb, },

    { 0, 0x100, 1, .write = xen_platform_ioport_writeb, },

    PORTIO_END_OF_LIST()

};



static const MemoryRegionOps xen_pci_io_ops = {

    .old_portio = xen_pci_portio,

    .read  = xen_platform_ioport_readb,

    .write = xen_platform_ioport_writeb,

    .impl.min_access_size = 1,

    .impl.max_access_size = 1,

};



static void platform_ioport_bar_setup(PCIXenPlatformState *d)