Commit 8e2d5831 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Aleksandar Markovic
Browse files

target/mips: Legalize Loongson insn flags 



To match the actual status of Loongson insn, we split flags
for LMMI and LEXT from INSN_LOONGSON2F.

As Loongson-2F only implemented interger part of LEXT, we'll
not enable LEXT for the processor, but instead we're still using
INSN_LOONGSON2F as switch flag of these instructions.

All multimedia instructions have been moved to LMMI flag. Loongson-2F
and Loongson-3A are sharing these instructions.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200614080049.31134-2-jiaxun.yang@flygoat.com>
parent 7d3660e7

target/mips/mips-defs.h

+2 −2
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ 
#define CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)

#define CPU_R5900       (CPU_MIPS3 | INSN_R5900)

#define CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)

#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)

#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)



#define CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
@@ -97,7 +97,7 @@ 
/* Wave Computing: "nanoMIPS" */

#define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)



#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A)

#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)



/*

 * Strictly follow the architecture standard:

target/mips/translate.c

+7 −6
Original line number Diff line number Diff line
@@ -1046,7 +1046,7 @@ enum { 
    OPC_BC2NEZ  = (0x0D << 21) | OPC_CP2,

};









#define MASK_LMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))









#define MASK_LMMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))

















enum {









    OPC_PADDSH      = (24 << 21) | (0x00) | OPC_CP2,








@@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,







    TCGv t0, t1, t2;









    int mem_idx = ctx->mem_idx;

















    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {









    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |









                                      INSN_LOONGSON3A)) {









        /*









         * Loongson CPU uses a load to zero register for prefetch.









         * We emulate it as a NOP. On other CPU we must perform the








@@ -5531,7 +5532,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)







    TCGv_i64 t0, t1;









    TCGCond cond;

















    opc = MASK_LMI(ctx->opcode);









    opc = MASK_LMMI(ctx->opcode);









    switch (opc) {









    case OPC_ADD_CP2:









    case OPC_SUB_CP2:








@@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)







    case OPC_MULTU_G_2F:









    case OPC_MOD_G_2F:









    case OPC_MODU_G_2F:









        check_insn(ctx, INSN_LOONGSON2F);









        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);









        gen_loongson_integer(ctx, op1, rd, rs, rt);









        break;









    case OPC_CLO:








@@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)







    case OPC_DDIVU_G_2F:









    case OPC_DMOD_G_2F:









    case OPC_DMODU_G_2F:









        check_insn(ctx, INSN_LOONGSON2F);









        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);









        gen_loongson_integer(ctx, op1, rd, rs, rt);









        break;









#endif








@@ -30641,7 +30642,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)







        }









        break;









    case OPC_CP2:









        check_insn(ctx, INSN_LOONGSON2F);









        check_insn(ctx, ASE_LMMI);









        /* Note that these instructions use different fields.  */









        gen_loongson_multimedia(ctx, sa, rd, rt);









        break;