Commit 8dae4697 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Tidy conditions in handle_vec_simd_shri 



The (size > 3 && !is_q) condition is identical to the preceeding test
of bit 3 in immh; eliminate it.  For the benefit of Coverity, assert
that size is within the bounds we expect.

Fixes: Coverity CID1385846
Fixes: Coverity CID1385849
Fixes: Coverity CID1385852
Fixes: Coverity CID1385857
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 20180501180455.11214-2-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 0c949276

target/arm/translate-a64.c

+1 −5
Original line number Diff line number Diff line
@@ -9019,11 +9019,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, 
        unallocated_encoding(s);

        return;

    }



    if (size > 3 && !is_q) {

        unallocated_encoding(s);

        return;

    }

    tcg_debug_assert(size <= 3);



    if (!fp_access_check(s)) {

        return;