Commit 8d927f7c authored by Fredrik Noring's avatar Fredrik Noring Committed by Aleksandar Markovic
Browse files

target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions 



Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarFredrik Noring <noring@nocrew.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 06de726b

target/mips/translate.c

+17 −6
Original line number Diff line number Diff line
@@ -4229,17 +4229,21 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, 
/* Arithmetic on HI/LO registers */

static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)

{

    if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {

    if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 ||

                     opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) {

        /* Treat as NOP. */

        return;

    }









    if (acc != 0) {









        if (!(ctx->insn_flags & INSN_R5900)) {









            check_dsp(ctx);









        }









    }

















    switch (opc) {









    case OPC_MFHI:









    case TX79_MMI_MFHI1:









#if defined(TARGET_MIPS64)









        if (acc != 0) {









            tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);








@@ -4250,6 +4254,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)







        }









        break;









    case OPC_MFLO:









    case TX79_MMI_MFLO1:









#if defined(TARGET_MIPS64)









        if (acc != 0) {









            tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);








@@ -4260,6 +4265,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)







        }









        break;









    case OPC_MTHI:









    case TX79_MMI_MTHI1:









        if (reg != 0) {









#if defined(TARGET_MIPS64)









            if (acc != 0) {








@@ -4274,6 +4280,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)







        }









        break;









    case OPC_MTLO:









    case TX79_MMI_MTLO1:









        if (reg != 0) {









#if defined(TARGET_MIPS64)









            if (acc != 0) {








@@ -24658,13 +24665,17 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)







    case TX79_MMI_MULTU1:









        gen_mul_txx9(ctx, opc, rd, rs, rt);









        break;









    case TX79_MMI_MTLO1:









    case TX79_MMI_MTHI1:









        gen_HILO(ctx, opc, 1, rs);









        break;









    case TX79_MMI_MFLO1:









    case TX79_MMI_MFHI1:









        gen_HILO(ctx, opc, 1, rd);









        break;









    case TX79_MMI_MADD:          /* TODO: TX79_MMI_MADD */









    case TX79_MMI_MADDU:         /* TODO: TX79_MMI_MADDU */









    case TX79_MMI_PLZCW:         /* TODO: TX79_MMI_PLZCW */









    case TX79_MMI_MFHI1:         /* TODO: TX79_MMI_MFHI1 */









    case TX79_MMI_MTHI1:         /* TODO: TX79_MMI_MTHI1 */









    case TX79_MMI_MFLO1:         /* TODO: TX79_MMI_MFLO1 */









    case TX79_MMI_MTLO1:         /* TODO: TX79_MMI_MTLO1 */









    case TX79_MMI_DIV1:          /* TODO: TX79_MMI_DIV1 */









    case TX79_MMI_DIVU1:         /* TODO: TX79_MMI_DIVU1 */









    case TX79_MMI_MADD1:         /* TODO: TX79_MMI_MADD1 */