Commit 8d031cec authored by Pu Wen's avatar Pu Wen Committed by Eduardo Habkost
Browse files

i386: Add new Hygon 'Dhyana' CPU model 

Add a new base CPU model called 'Dhyana' to model processors from Hygon
Dhyana(family 18h), which derived from AMD EPYC(family 17h).

The following features bits have been removed compare to AMD EPYC:
aes, pclmulqdq, sha_ni

The Hygon Dhyana support to KVM in Linux is already accepted upstream[1].
So add Hygon Dhyana support to Qemu is necessary to create Hygon's own
CPU model.

Reference:
[1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87



Signed-off-by: default avatarPu Wen <puwen@hygon.cn>
Message-Id: <1555416373-28690-1-git-send-email-puwen@hygon.cn>
Reviewed-by: default avatarDaniel P. Berrangé <berrange@redhat.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 3284aa12

target/i386/cpu.c

+50 −0
Original line number Diff line number Diff line
@@ -2935,6 +2935,56 @@ static X86CPUDefinition builtin_x86_defs[] = { 
        .model_id = "AMD EPYC Processor (with IBPB)",

        .cache_info = &epyc_cache_info,

    },

    {

        .name = "Dhyana",

        .level = 0xd,

        .vendor = CPUID_VENDOR_HYGON,

        .family = 24,

        .model = 0,

        .stepping = 1,

        .features[FEAT_1_EDX] =

            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |

            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |

            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |

            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |

            CPUID_VME | CPUID_FP87,

        .features[FEAT_1_ECX] =

            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |

            CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |

            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |

            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |

            CPUID_EXT_MONITOR | CPUID_EXT_SSE3,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |

            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |

            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |

            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |

            CPUID_EXT3_TOPOEXT,

        .features[FEAT_8000_0008_EBX] =

            CPUID_8000_0008_EBX_IBPB,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |

            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |

            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,

        /*

         * Missing: XSAVES (not supported by some Linux versions,

         * including v4.1 to v4.12).

         * KVM doesn't yet expose any XSAVES state save component.

         */

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |

            CPUID_XSAVE_XGETBV1,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .features[FEAT_SVM] =

            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,

        .xlevel = 0x8000001E,

        .model_id = "Hygon Dhyana Processor",

        .cache_info = &epyc_cache_info,

    },

};



typedef struct PropValue {

target/i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -726,6 +726,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 


#define CPUID_VENDOR_VIA   "CentaurHauls"



#define CPUID_VENDOR_HYGON    "HygonGenuine"



#define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */

#define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */