Commit 8ca19bd8 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging 



target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transaction_failed and add test for failed memory
  transactions;
- fix couple FPU2000 bugs;
- fix s32c1i implementation;
- clean up exception handlers generation in xtensa tests;
- add support for semihosting console input through a chardev.

# gpg: Signature made Tue 18 Sep 2018 18:35:50 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180918-xtensa:
  target/xtensa: support input from chardev console
  target/xtensa: fix s32c1i TCGMemOp flags
  tests/tcg/xtensa: only generate defined exception handlers
  tests/tcg/xtensa: move exception handlers to separate section
  target/xtensa: fix FPU2000 bugs
  tests/tcg/xtensa: add test for failed memory transactions
  target/xtensa: convert to do_transaction_failed
  target/xtensa: add test_kc705_be core
  target/xtensa: clean up gdbstub register handling
  target/xtensa: fix gdbstub register counts

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 5b9000b5 5aa37f48

target/xtensa/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ obj-y += core-dc233c.o 
obj-y += core-de212.o

obj-y += core-fsf.o

obj-y += core-sample_controller.o

obj-y += core-test_kc705_be.o

obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o

obj-y += xtensa-isa.o

obj-y += translate.o op_helper.o helper.o cpu.o

target/xtensa/core-test_kc705_be.c

0 → 100644
+52 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include "qemu/osdep.h"

#include "cpu.h"

#include "exec/gdbstub.h"

#include "qemu-common.h"

#include "qemu/host-utils.h"



#include "core-test_kc705_be/core-isa.h"

#include "overlay_tool.h"



#define xtensa_modules xtensa_modules_test_kc705_be

#include "core-test_kc705_be/xtensa-modules.inc.c"



static XtensaConfig test_kc705_be __attribute__((unused)) = {

    .name = "test_kc705_be",

    .gdb_regmap = {

        .reg = {

#include "core-test_kc705_be/gdb-config.inc.c"

        }

    },

    .isa_internal = &xtensa_modules,

    .clock_freq_khz = 40000,

    DEFAULT_SECTIONS

};



REGISTER_CORE(test_kc705_be)

target/xtensa/core-test_kc705_be/core-isa.h

0 → 100644
+575 −0

File added.

Preview size limit exceeded, changes collapsed.

target/xtensa/core-test_kc705_be/gdb-config.inc.c

0 → 100644
+259 −0
Original line number Diff line number Diff line 
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.



   Copyright (c) 2003-2015 Tensilica Inc.



   Permission is hereby granted, free of charge, to any person obtaining

   a copy of this software and associated documentation files (the

   "Software"), to deal in the Software without restriction, including

   without limitation the rights to use, copy, modify, merge, publish,

   distribute, sublicense, and/or sell copies of the Software, and to

   permit persons to whom the Software is furnished to do so, subject to

   the following conditions:



   The above copyright notice and this permission notice shall be included

   in all copies or substantial portions of the Software.



   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */

  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc,          0,0,0,0,0,0)

  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,         0,0,0,0,0,0)

  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,         0,0,0,0,0,0)

  XTREG(  3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2,         0,0,0,0,0,0)

  XTREG(  4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3,         0,0,0,0,0,0)

  XTREG(  5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4,         0,0,0,0,0,0)

  XTREG(  6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5,         0,0,0,0,0,0)

  XTREG(  7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6,         0,0,0,0,0,0)

  XTREG(  8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7,         0,0,0,0,0,0)

  XTREG(  9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8,         0,0,0,0,0,0)

  XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9,         0,0,0,0,0,0)

  XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10,        0,0,0,0,0,0)

  XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11,        0,0,0,0,0,0)

  XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12,        0,0,0,0,0,0)

  XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13,        0,0,0,0,0,0)

  XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14,        0,0,0,0,0,0)

  XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15,        0,0,0,0,0,0)

  XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16,        0,0,0,0,0,0)

  XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17,        0,0,0,0,0,0)

  XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18,        0,0,0,0,0,0)

  XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19,        0,0,0,0,0,0)

  XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20,        0,0,0,0,0,0)

  XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21,        0,0,0,0,0,0)

  XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22,        0,0,0,0,0,0)

  XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23,        0,0,0,0,0,0)

  XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24,        0,0,0,0,0,0)

  XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25,        0,0,0,0,0,0)

  XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26,        0,0,0,0,0,0)

  XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27,        0,0,0,0,0,0)

  XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28,        0,0,0,0,0,0)

  XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29,        0,0,0,0,0,0)

  XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30,        0,0,0,0,0,0)

  XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31,        0,0,0,0,0,0)

  XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg,        0,0,0,0,0,0)

  XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend,        0,0,0,0,0,0)

  XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount,      0,0,0,0,0,0)

  XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar,         0,0,0,0,0,0)

  XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl,     0,0,0,0,0,0)

  XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase,  0,0,0,0,0,0)

  XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)

  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)

  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)

  XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,          0,0,0,0,0,0)

  XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,   0,0,0,0,0,0)

  XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br,          0,0,0,0,0,0)

  XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1,   0,0,0,0,0,0)

  XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo,       0,0,0,0,0,0)

  XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi,       0,0,0,0,0,0)

  XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0,          0,0,0,0,0,0)

  XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1,          0,0,0,0,0,0)

  XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2,          0,0,0,0,0,0)

  XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3,          0,0,0,0,0,0)

  XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate,    0,0,0,0,0,0)

  XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,

            "03:40:48:2b","03:40:48:7a",0,0,0,0)

  XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,

            "03:40:49:2b","03:40:49:7a",0,0,0,0)

  XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,

            "03:40:4a:2b","03:40:4a:7a",0,0,0,0)

  XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,

            "03:40:4b:2b","03:40:4b:7a",0,0,0,0)

  XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,

            "03:40:4c:2b","03:40:4c:7a",0,0,0,0)

  XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,

            "03:40:4d:2b","03:40:4d:7a",0,0,0,0)

  XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,

            "03:40:4e:2b","03:40:4e:7a",0,0,0,0)

  XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,

            "03:40:4f:2b","03:40:4f:7a",0,0,0,0)

  XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,

            "03:40:40:3c","03:40:40:1c",0,0,0,0)

  XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,

            "03:40:41:3c","03:40:44:1c",0,0,0,0)

  XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,

            "03:40:42:3c","03:40:48:1c",0,0,0,0)

  XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,

            "03:40:43:3c","03:40:4c:1c",0,0,0,0)

  XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar,  0,0,0,0,0,0)

  XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead,  0,0,0,0,0,0)

  XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)

  XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no,    0,0,0,0,0,0)

  XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0,  0,0,0,0,0,0)

  XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0,    0,0,0,0,0,0)

  XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr,    0,0,0,0,0,0)

  XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid,        0,0,0,0,0,0)

  XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid,       0,0,0,0,0,0)

  XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg,     0,0,0,0,0,0)

  XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg,     0,0,0,0,0,0)

  XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)

  XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl,     0,0,0,0,0,0)

  XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr,         0,0,0,0,0,0)

  XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0,    0,0,0,0,0,0)

  XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1,    0,0,0,0,0,0)

  XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0,    0,0,0,0,0,0)

  XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1,    0,0,0,0,0,0)

  XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0,    0,0,0,0,0,0)

  XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1,    0,0,0,0,0,0)

  XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1,        0,0,0,0,0,0)

  XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2,        0,0,0,0,0,0)

  XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3,        0,0,0,0,0,0)

  XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4,        0,0,0,0,0,0)

  XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5,        0,0,0,0,0,0)

  XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6,        0,0,0,0,0,0)

  XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7,        0,0,0,0,0,0)

  XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc,        0,0,0,0,0,0)

  XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2,        0,0,0,0,0,0)

  XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3,        0,0,0,0,0,0)

  XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4,        0,0,0,0,0,0)

  XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5,        0,0,0,0,0,0)

  XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6,        0,0,0,0,0,0)

  XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7,        0,0,0,0,0,0)

  XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1,    0,0,0,0,0,0)

  XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2,    0,0,0,0,0,0)

  XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3,    0,0,0,0,0,0)

  XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4,    0,0,0,0,0,0)

  XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5,    0,0,0,0,0,0)

  XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6,    0,0,0,0,0,0)

  XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7,    0,0,0,0,0,0)

  XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable,    0,0,0,0,0,0)

  XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt,   0,0,0,0,0,0)

  XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset,      0,0,0,0,0,0)

  XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear,    0,0,0,0,0,0)

  XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable,   0,0,0,0,0,0)

  XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase,     0,0,0,0,0,0)

  XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause,    0,0,0,0,0,0)

  XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause,  0,0,0,0,0,0)

  XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount,      0,0,0,0,0,0)

  XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid,        0,0,0,0,0,0)

  XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount,      0,0,0,0,0,0)

  XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)

  XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr,    0,0,0,0,0,0)

  XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0,   0,0,0,0,0,0)

  XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1,   0,0,0,0,0,0)

  XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2,   0,0,0,0,0,0)

  XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0,       0,0,0,0,0,0)

  XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1,       0,0,0,0,0,0)

  XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0,          0,0,0,0,0,0)

  XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1,          0,0,0,0,0,0)

  XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2,          0,0,0,0,0,0)

  XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3,          0,0,0,0,0,0)

  XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4,          0,0,0,0,0,0)

  XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5,          0,0,0,0,0,0)

  XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6,          0,0,0,0,0,0)

  XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7,          0,0,0,0,0,0)

  XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8,          0,0,0,0,0,0)

  XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9,          0,0,0,0,0,0)

  XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10,         0,0,0,0,0,0)

  XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11,         0,0,0,0,0,0)

  XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12,         0,0,0,0,0,0)

  XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13,         0,0,0,0,0,0)

  XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14,         0,0,0,0,0,0)

  XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15,         0,0,0,0,0,0)

  XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,

            0,0,&xtensa_mask0,0,0,0)

  XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,

            0,0,&xtensa_mask1,0,0,0)

  XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,

            0,0,&xtensa_mask2,0,0,0)

  XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,

            0,0,&xtensa_mask3,0,0,0)

  XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,

            0,0,&xtensa_mask4,0,0,0)

  XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,

            0,0,&xtensa_mask5,0,0,0)

  XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,

            0,0,&xtensa_mask6,0,0,0)

  XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,

            0,0,&xtensa_mask7,0,0,0)

  XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,

            0,0,&xtensa_mask8,0,0,0)

  XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,

            0,0,&xtensa_mask9,0,0,0)

  XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,

            0,0,&xtensa_mask10,0,0,0)

  XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,

            0,0,&xtensa_mask11,0,0,0)

  XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,

            0,0,&xtensa_mask12,0,0,0)

  XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,

            0,0,&xtensa_mask13,0,0,0)

  XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,

            0,0,&xtensa_mask14,0,0,0)

  XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,

            0,0,&xtensa_mask15,0,0,0)

  XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,

            0,0,&xtensa_mask16,0,0,0)

  XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,

            0,0,&xtensa_mask17,0,0,0)

  XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,

            0,0,&xtensa_mask18,0,0,0)

  XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,

            0,0,&xtensa_mask19,0,0,0)

  XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,

            0,0,&xtensa_mask20,0,0,0)

  XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,

            0,0,&xtensa_mask21,0,0,0)

  XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,

            0,0,&xtensa_mask22,0,0,0)

  XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,

            0,0,&xtensa_mask23,0,0,0)

  XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,

            0,0,&xtensa_mask24,0,0,0)

  XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,

            0,0,&xtensa_mask25,0,0,0)

  XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,

            0,0,&xtensa_mask26,0,0,0)

  XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,

            0,0,&xtensa_mask27,0,0,0)

  XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6,

            0,0,&xtensa_mask28,0,0,0)

  XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5,

            0,0,&xtensa_mask29,0,0,0)

  XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4,

            0,0,&xtensa_mask30,0,0,0)

  XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6,

            0,0,&xtensa_mask31,0,0,0)

  XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5,

            0,0,&xtensa_mask32,0,0,0)

  XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4,

            0,0,&xtensa_mask33,0,0,0)

  XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase,

            0,0,&xtensa_mask34,0,0,0)

  XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow,

            0,0,&xtensa_mask35,0,0,0)

  XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar,

            0,0,&xtensa_mask36,0,0,0)

  XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr,

            0,0,&xtensa_mask37,0,0,0)

  XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused,

            0,0,&xtensa_mask38,0,0,0)

  XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize,

            0,0,&xtensa_mask39,0,0,0)

  XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts,

            0,0,&xtensa_mask40,0,0,0)

  XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset,

            0,0,&xtensa_mask41,0,0,0)

  XTREG_END

target/xtensa/core-test_kc705_be/xtensa-modules.inc.c

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