Commit 8c949951 authored by Stafford Horne's avatar Stafford Horne
Browse files

target/openrisc: Make coreid and numcores variable 



Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent 0ca9fa2e

target/openrisc/sys_helper.c

+3 −2
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "exec/exec-all.h"

#include "exec/helper-proto.h"

#include "exception.h"

#include "sysemu/sysemu.h"



#define TO_SPR(group, number) (((group) << 11) + (number))
@@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, 
        return env->esr;



    case TO_SPR(0, 128): /* COREID */

        return 0;

        return cpu->parent_obj.cpu_index;



    case TO_SPR(0, 129): /* NUMCORES */

        return 1;

        return max_cpus;



    case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */

        idx = (spr - 1024);