Commit 8bfc26ea authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make CONTROL register banked for v8M 



Make the CONTROL register banked if v8M security extensions are enabled.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org
parent 42a6686b

target/arm/cpu.h

+3 −2
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ typedef struct CPUARMState { 
        uint32_t other_sp;

        uint32_t vecbase;

        uint32_t basepri[2];

        uint32_t control;

        uint32_t control[2];

        uint32_t ccr; /* Configuration and Control */

        uint32_t cfsr; /* Configurable Fault Status */

        uint32_t hfsr; /* HardFault Status */
@@ -1681,7 +1681,8 @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 
static inline int arm_current_el(CPUARMState *env)

{

    if (arm_feature(env, ARM_FEATURE_M)) {

        return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1);

        return arm_v7m_is_handler_mode(env) ||

            !(env->v7m.control[env->v7m.secure] & 1);

    }



    if (is_a64(env)) {

target/arm/helper.c

+11 −10
Original line number Diff line number Diff line
@@ -6048,14 +6048,15 @@ static uint32_t v7m_pop(CPUARMState *env) 
static void switch_v7m_sp(CPUARMState *env, bool new_spsel)

{

    uint32_t tmp;

    bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK;

    uint32_t old_control = env->v7m.control[env->v7m.secure];

    bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK;



    if (old_spsel != new_spsel) {

        tmp = env->v7m.other_sp;

        env->v7m.other_sp = env->regs[13];

        env->regs[13] = tmp;



        env->v7m.control = deposit32(env->v7m.control,

        env->v7m.control[env->v7m.secure] = deposit32(old_control,

                                     R_V7M_CONTROL_SPSEL_SHIFT,

                                     R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);

    }
@@ -6409,7 +6410,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) 
    }



    lr = 0xfffffff1;

    if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {

    if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {

        lr |= 4;

    }

    if (!arm_v7m_is_handler_mode(env)) {
@@ -8827,7 +8828,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 
        return xpsr_read(env) & mask;

        break;

    case 20: /* CONTROL */

        return env->v7m.control;

        return env->v7m.control[env->v7m.secure];

    }



    if (el == 0) {
@@ -8836,10 +8837,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 


    switch (reg) {

    case 8: /* MSP */

        return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?

        return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?

            env->v7m.other_sp : env->regs[13];

    case 9: /* PSP */

        return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?

        return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?

            env->regs[13] : env->v7m.other_sp;

    case 16: /* PRIMASK */

        return env->v7m.primask[env->v7m.secure];
@@ -8888,14 +8889,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) 
        }

        break;

    case 8: /* MSP */

        if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {

        if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {

            env->v7m.other_sp = val;

        } else {

            env->regs[13] = val;

        }

        break;

    case 9: /* PSP */

        if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {

        if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {

            env->regs[13] = val;

        } else {

            env->v7m.other_sp = val;
@@ -8926,8 +8927,8 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) 
        if (!arm_v7m_is_handler_mode(env)) {

            switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);

        }

        env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;

        env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;

        env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;

        env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"

target/arm/machine.c

+2 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static const VMStateDescription vmstate_m = { 
    .fields = (VMStateField[]) {

        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),

        VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.control, ARMCPU),

        VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.ccr, ARMCPU),

        VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),

        VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
@@ -253,6 +253,7 @@ static const VMStateDescription vmstate_m_security = { 
        VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),

        VMSTATE_END_OF_LIST()

    }

};

target/arm/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -12241,7 +12241,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 
        if (xpsr & XPSR_EXCP) {

            mode = "handler";

        } else {

            if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) {

            if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {

                mode = "unpriv-thread";

            } else {

                mode = "priv-thread";