Loading cpu-common.h +0 −5 Original line number Diff line number Diff line Loading @@ -39,10 +39,6 @@ typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); /* This should only be used for ram local to a device. */ void *qemu_get_ram_ptr(ram_addr_t addr); void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size); /* Same but slower, to use for migration, where the order of * RAMBlocks must not change. */ void *qemu_safe_ram_ptr(ram_addr_t addr); void qemu_put_ram_ptr(void *addr); /* This should not be used by devices. */ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); Loading @@ -67,7 +63,6 @@ void *cpu_physical_memory_map(hwaddr addr, void cpu_physical_memory_unmap(void *buffer, hwaddr len, int is_write, hwaddr access_len); void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); void cpu_unregister_map_client(void *cookie); bool cpu_physical_memory_is_io(hwaddr phys_addr); Loading exec-all.h +0 −2 Original line number Diff line number Diff line Loading @@ -194,8 +194,6 @@ static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) void tb_free(TranslationBlock *tb); void tb_flush(CPUArchState *env); void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; Loading exec.c +9 −6 Original line number Diff line number Diff line Loading @@ -188,9 +188,12 @@ static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; static void io_mem_init(void); static void memory_map_init(void); static void *qemu_safe_ram_ptr(ram_addr_t addr); static MemoryRegion io_mem_watch; #endif static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); /* statistics */ static int tb_flush_count; Loading Loading @@ -1349,8 +1352,8 @@ static inline void tb_alloc_page(TranslationBlock *tb, /* add a new TB and link it to the physical page tables. phys_page2 is (-1) to indicate that only one page contains the TB. */ void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) { unsigned int h; TranslationBlock **ptb; Loading Loading @@ -1859,7 +1862,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, } } int cpu_physical_memory_set_dirty_tracking(int enable) static int cpu_physical_memory_set_dirty_tracking(int enable) { int ret = 0; in_migration = enable; Loading Loading @@ -2741,7 +2744,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr) /* Return a host pointer to ram allocated with qemu_ram_alloc. * Same as qemu_get_ram_ptr but avoid reordering ramblocks. */ void *qemu_safe_ram_ptr(ram_addr_t addr) static void *qemu_safe_ram_ptr(ram_addr_t addr) { RAMBlock *block; Loading Loading @@ -2771,7 +2774,7 @@ void *qemu_safe_ram_ptr(ram_addr_t addr) /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr * but takes a size argument */ void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) { if (*size == 0) { return NULL; Loading Loading @@ -3519,7 +3522,7 @@ void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) return client; } void cpu_unregister_map_client(void *_client) static void cpu_unregister_map_client(void *_client) { MapClient *client = (MapClient *)_client; Loading memory-internal.h +0 −2 Original line number Diff line number Diff line Loading @@ -55,8 +55,6 @@ struct MemoryRegionSection; void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size); void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size); int cpu_physical_memory_set_dirty_tracking(int enable); #define VGA_DIRTY_FLAG 0x01 #define CODE_DIRTY_FLAG 0x02 #define MIGRATION_DIRTY_FLAG 0x08 Loading Loading
cpu-common.h +0 −5 Original line number Diff line number Diff line Loading @@ -39,10 +39,6 @@ typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); /* This should only be used for ram local to a device. */ void *qemu_get_ram_ptr(ram_addr_t addr); void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size); /* Same but slower, to use for migration, where the order of * RAMBlocks must not change. */ void *qemu_safe_ram_ptr(ram_addr_t addr); void qemu_put_ram_ptr(void *addr); /* This should not be used by devices. */ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); Loading @@ -67,7 +63,6 @@ void *cpu_physical_memory_map(hwaddr addr, void cpu_physical_memory_unmap(void *buffer, hwaddr len, int is_write, hwaddr access_len); void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); void cpu_unregister_map_client(void *cookie); bool cpu_physical_memory_is_io(hwaddr phys_addr); Loading
exec-all.h +0 −2 Original line number Diff line number Diff line Loading @@ -194,8 +194,6 @@ static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) void tb_free(TranslationBlock *tb); void tb_flush(CPUArchState *env); void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; Loading
exec.c +9 −6 Original line number Diff line number Diff line Loading @@ -188,9 +188,12 @@ static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; static void io_mem_init(void); static void memory_map_init(void); static void *qemu_safe_ram_ptr(ram_addr_t addr); static MemoryRegion io_mem_watch; #endif static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); /* statistics */ static int tb_flush_count; Loading Loading @@ -1349,8 +1352,8 @@ static inline void tb_alloc_page(TranslationBlock *tb, /* add a new TB and link it to the physical page tables. phys_page2 is (-1) to indicate that only one page contains the TB. */ void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) { unsigned int h; TranslationBlock **ptb; Loading Loading @@ -1859,7 +1862,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, } } int cpu_physical_memory_set_dirty_tracking(int enable) static int cpu_physical_memory_set_dirty_tracking(int enable) { int ret = 0; in_migration = enable; Loading Loading @@ -2741,7 +2744,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr) /* Return a host pointer to ram allocated with qemu_ram_alloc. * Same as qemu_get_ram_ptr but avoid reordering ramblocks. */ void *qemu_safe_ram_ptr(ram_addr_t addr) static void *qemu_safe_ram_ptr(ram_addr_t addr) { RAMBlock *block; Loading Loading @@ -2771,7 +2774,7 @@ void *qemu_safe_ram_ptr(ram_addr_t addr) /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr * but takes a size argument */ void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) { if (*size == 0) { return NULL; Loading Loading @@ -3519,7 +3522,7 @@ void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) return client; } void cpu_unregister_map_client(void *_client) static void cpu_unregister_map_client(void *_client) { MapClient *client = (MapClient *)_client; Loading
memory-internal.h +0 −2 Original line number Diff line number Diff line Loading @@ -55,8 +55,6 @@ struct MemoryRegionSection; void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size); void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size); int cpu_physical_memory_set_dirty_tracking(int enable); #define VGA_DIRTY_FLAG 0x01 #define CODE_DIRTY_FLAG 0x02 #define MIGRATION_DIRTY_FLAG 0x08 Loading