Commit 8b92b9ef authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200527' into staging 



ppc patch queue 2020-05-27

Here's the next pull request for qemu-5.1.  It includes:
 * Support for the scv and rfscv POWER9 instructions in TCG
 * Support for the new SPAPR_LMB_FLAGS_HOTREMOVABLE flag, which
   provides a way for guests to know memory which should be removable
   (so the guest can avoid putting immovable allocations there).
 * Some fixes for the recently added partition scope radix translation
   in softmmu
 * Assorted minor fixes and cleanups

It includes one patch to avoid a clash with SELinux when using NVLink
VFIO devices.  That's not technically within the files under my
maintainership, but it is in a section of the VFIO quirks code that's
specific to the POWER-only NVLink devices, and has an ack from Alex
Williamson.

# gpg: Signature made Wed 27 May 2020 06:36:59 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.1-20200527:
  vfio/nvlink: Remove exec permission to avoid SELinux AVCs
  target/ppc: Fix argument to ppc_radix64_partition_scoped_xlate() again
  hw/nvram/mac_nvram: Convert debug printf()s to trace events
  hw/pci-bridge/dec: Remove dead debug code
  target/ppc: Don't update radix PTE R/C bits with gdbstub
  target/ppc: Fix arguments to ppc_radix64_partition_scoped_xlate()
  target/ppc: Add missing braces in ppc_radix64_partition_scoped_xlate()
  target/ppc: Don't initialize some local variables in ppc_radix64_xlate()
  target/ppc: Pass const pointer to ppc_radix64_get_fully_qualified_addr()
  target/ppc: Pass const pointer to ppc_radix64_get_prot_amr()
  ppc/spapr: Add hotremovable flag on DIMM LMBs on drmem_v2
  target/ppc: Add support for scv and rfscv instructions
  target/ppc: Untabify excp_helper.c
  ppc/spapr: add a POWER10 CPU model
  ppc/pnv: Fix NMI system reset SRR1 value

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 06539ebc 9c7c0407

hw/nvram/mac_nvram.c

+3 −14
Original line number Diff line number Diff line
@@ -30,18 +30,9 @@ 
#include "migration/vmstate.h"

#include "qemu/cutils.h"

#include "qemu/module.h"

#include "trace.h"

#include <zlib.h>



/* debug NVR */

//#define DEBUG_NVR



#ifdef DEBUG_NVR

#define NVR_DPRINTF(fmt, ...)                                   \

    do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)

#else

#define NVR_DPRINTF(fmt, ...)

#endif



#define DEF_SYSTEM_SIZE 0xc10



/* macio style NVRAM device */
@@ -51,9 +42,8 @@ static void macio_nvram_writeb(void *opaque, hwaddr addr, 
    MacIONVRAMState *s = opaque;



    addr = (addr >> s->it_shift) & (s->size - 1);

    trace_macio_nvram_write(addr, value);

    s->data[addr] = value;

    NVR_DPRINTF("writeb addr %04" HWADDR_PRIx " val %" PRIx64 "\n",

                addr, value);

}



static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
@@ -64,8 +54,7 @@ static uint64_t macio_nvram_readb(void *opaque, hwaddr addr, 


    addr = (addr >> s->it_shift) & (s->size - 1);

    value = s->data[addr];

    NVR_DPRINTF("readb addr %04" HWADDR_PRIx " val %" PRIx32 "\n",

                addr, value);

    trace_macio_nvram_read(addr, value);



    return value;

}

hw/nvram/trace-events

+4 −0
Original line number Diff line number Diff line
@@ -13,3 +13,7 @@ fw_cfg_add_string(uint16_t key_value, const char *key_name, const char *value) " 
fw_cfg_add_i16(uint16_t key_value, const char *key_name, uint16_t value) "key 0x%04" PRIx16 " '%s', value 0x%" PRIx16

fw_cfg_add_i32(uint16_t key_value, const char *key_name, uint32_t value) "key 0x%04" PRIx16 " '%s', value 0x%" PRIx32

fw_cfg_add_i64(uint16_t key_value, const char *key_name, uint64_t value) "key 0x%04" PRIx16 " '%s', value 0x%" PRIx64



# mac_nvram.c

macio_nvram_read(uint32_t addr, uint8_t val) "read addr=0x%04"PRIx32" val=0x%02x"

macio_nvram_write(uint32_t addr, uint8_t val) "write addr=0x%04"PRIx32" val=0x%02x"

hw/pci-bridge/dec.c

+0 −10
Original line number Diff line number Diff line
@@ -32,16 +32,6 @@ 
#include "hw/pci/pci_bridge.h"

#include "hw/pci/pci_bus.h"



/* debug DEC */

//#define DEBUG_DEC



#ifdef DEBUG_DEC

#define DEC_DPRINTF(fmt, ...)                               \

    do { printf("DEC: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DEC_DPRINTF(fmt, ...)

#endif



#define DEC_21154(obj) OBJECT_CHECK(DECState, (obj), TYPE_DEC_21154)



typedef struct DECState {

hw/ppc/pnv.c

+20 −6
Original line number Diff line number Diff line
@@ -1984,12 +1984,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 


    cpu_synchronize_state(cs);

    ppc_cpu_do_system_reset(cs);

    if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {

        /*

     * SRR1[42:45] is set to 0100 which the ISA defines as implementation

     * dependent. POWER processors use this for xscom triggered interrupts,

     * which come from the BMC or NMI IPIs.

         * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the

         * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100

         * (PPC_BIT(43)).

         */

    env->spr[SPR_SRR1] |= PPC_BIT(43);

        if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {

            warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");

            env->spr[SPR_SRR1] |= SRR1_WAKERESET;

        }

    } else {

        /*

         * For non-powersave system resets, SRR1[42:45] are defined to be

         * implementation-dependent. The POWER9 User Manual specifies that

         * an external (SCOM driven, which may come from a BMC nmi command or

         * another CPU requesting a NMI IPI) system reset exception should be

         * 0b0010 (PPC_BIT(44)).

         */

        env->spr[SPR_SRR1] |= SRR1_WAKESCOM;

    }

}



static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)

hw/ppc/spapr.c

+2 −1
Original line number Diff line number Diff line
@@ -445,7 +445,8 @@ static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 
        g_assert(drc);

        elem = spapr_get_drconf_cell(size / lmb_size, addr,

                                     spapr_drc_index(drc), node,

                                     SPAPR_LMB_FLAGS_ASSIGNED);

                                     (SPAPR_LMB_FLAGS_ASSIGNED |

                                      SPAPR_LMB_FLAGS_HOTREMOVABLE));

        QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);

        nr_entries++;

        cur_addr = addr + size;