Commit 8b20aefa authored by Prasad J Pandit's avatar Prasad J Pandit Committed by Peter Maydell
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sd: sdhci: mask transfer mode register value 



In SDHCI protocol, the transfer mode register is defined
to be of 6 bits. Mask its value with '0x0037' so that an
invalid value could not be assigned.

Signed-off-by: default avatarPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Message-id: 20170214185225.7994-2-ppandit@redhat.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 373442ea

hw/sd/sdhci.c

+2 −1
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
    (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \

    (SDHC_CAPAB_TOCLKFREQ))



#define MASK_TRNMOD     0x0037

#define MASKED_WRITE(reg, mask, val)  (reg = (reg & (mask)) | (val))



static uint8_t sdhci_slotint(SDHCIState *s)
@@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 
        if (!(s->capareg & SDHC_CAN_DO_DMA)) {

            value &= ~SDHC_TRNS_DMA;

        }

        MASKED_WRITE(s->trnmod, mask, value);

        MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);

        MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);



        /* Writing to the upper byte of CMDREG triggers SD command generation */