Loading hw/ide/ahci.c +15 −10 Original line number Diff line number Diff line Loading @@ -339,7 +339,7 @@ static void ahci_mem_write(void *opaque, target_phys_addr_t addr, case HOST_CTL: /* R/W */ if (val & HOST_CTL_RESET) { DPRINTF(-1, "HBA Reset\n"); ahci_reset(container_of(s, AHCIPCIState, ahci)); ahci_reset(s); } else { s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; ahci_check_irq(s); Loading Loading @@ -1149,21 +1149,20 @@ void ahci_uninit(AHCIState *s) g_free(s->dev); } void ahci_reset(void *opaque) void ahci_reset(AHCIState *s) { struct AHCIPCIState *d = opaque; AHCIPortRegs *pr; int i; d->ahci.control_regs.irqstatus = 0; d->ahci.control_regs.ghc = 0; s->control_regs.irqstatus = 0; s->control_regs.ghc = 0; for (i = 0; i < d->ahci.ports; i++) { pr = &d->ahci.dev[i].port_regs; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; pr->irq_stat = 0; pr->irq_mask = 0; pr->scr_ctl = 0; ahci_reset_port(&d->ahci, i); ahci_reset_port(s, i); } } Loading @@ -1178,6 +1177,13 @@ static const VMStateDescription vmstate_sysbus_ahci = { .unmigratable = 1, }; static void sysbus_ahci_reset(DeviceState *dev) { SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev); ahci_reset(&s->ahci); } static int sysbus_ahci_init(SysBusDevice *dev) { SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev); Loading @@ -1185,8 +1191,6 @@ static int sysbus_ahci_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->ahci.mem); sysbus_init_irq(dev, &s->ahci.irq); qemu_register_reset(ahci_reset, &s->ahci); return 0; } Loading @@ -1203,6 +1207,7 @@ static void sysbus_ahci_class_init(ObjectClass *klass, void *data) sbc->init = sysbus_ahci_init; dc->vmsd = &vmstate_sysbus_ahci; dc->props = sysbus_ahci_properties; dc->reset = sysbus_ahci_reset; } static TypeInfo sysbus_ahci_info = { Loading hw/ide/ahci.h +1 −1 Original line number Diff line number Diff line Loading @@ -332,6 +332,6 @@ typedef struct NCQFrame { void ahci_init(AHCIState *s, DeviceState *qdev, int ports); void ahci_uninit(AHCIState *s); void ahci_reset(void *opaque); void ahci_reset(AHCIState *s); #endif /* HW_IDE_AHCI_H */ hw/ide/ich.c +4 −6 Original line number Diff line number Diff line Loading @@ -84,12 +84,12 @@ static const VMStateDescription vmstate_ahci = { .unmigratable = 1, }; static void pci_ich9_reset(void *opaque) static void pci_ich9_reset(DeviceState *dev) { struct AHCIPCIState *d = opaque; struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev); msi_reset(&d->card); ahci_reset(opaque); ahci_reset(&d->ahci); } static int pci_ich9_ahci_init(PCIDevice *dev) Loading @@ -110,8 +110,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) /* XXX Software should program this register */ d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ qemu_register_reset(pci_ich9_reset, d); msi_init(dev, 0x50, 1, true, false); d->ahci.irq = d->card.irq[0]; Loading Loading @@ -141,7 +139,6 @@ static int pci_ich9_uninit(PCIDevice *dev) d = DO_UPCAST(struct AHCIPCIState, card, dev); msi_uninit(dev); qemu_unregister_reset(pci_ich9_reset, d); ahci_uninit(&d->ahci); return 0; Loading @@ -167,6 +164,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data) k->revision = 0x02; k->class_id = PCI_CLASS_STORAGE_SATA; dc->vmsd = &vmstate_ahci; dc->reset = pci_ich9_reset; } static TypeInfo ich_ahci_info = { Loading Loading
hw/ide/ahci.c +15 −10 Original line number Diff line number Diff line Loading @@ -339,7 +339,7 @@ static void ahci_mem_write(void *opaque, target_phys_addr_t addr, case HOST_CTL: /* R/W */ if (val & HOST_CTL_RESET) { DPRINTF(-1, "HBA Reset\n"); ahci_reset(container_of(s, AHCIPCIState, ahci)); ahci_reset(s); } else { s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; ahci_check_irq(s); Loading Loading @@ -1149,21 +1149,20 @@ void ahci_uninit(AHCIState *s) g_free(s->dev); } void ahci_reset(void *opaque) void ahci_reset(AHCIState *s) { struct AHCIPCIState *d = opaque; AHCIPortRegs *pr; int i; d->ahci.control_regs.irqstatus = 0; d->ahci.control_regs.ghc = 0; s->control_regs.irqstatus = 0; s->control_regs.ghc = 0; for (i = 0; i < d->ahci.ports; i++) { pr = &d->ahci.dev[i].port_regs; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; pr->irq_stat = 0; pr->irq_mask = 0; pr->scr_ctl = 0; ahci_reset_port(&d->ahci, i); ahci_reset_port(s, i); } } Loading @@ -1178,6 +1177,13 @@ static const VMStateDescription vmstate_sysbus_ahci = { .unmigratable = 1, }; static void sysbus_ahci_reset(DeviceState *dev) { SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev); ahci_reset(&s->ahci); } static int sysbus_ahci_init(SysBusDevice *dev) { SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev); Loading @@ -1185,8 +1191,6 @@ static int sysbus_ahci_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->ahci.mem); sysbus_init_irq(dev, &s->ahci.irq); qemu_register_reset(ahci_reset, &s->ahci); return 0; } Loading @@ -1203,6 +1207,7 @@ static void sysbus_ahci_class_init(ObjectClass *klass, void *data) sbc->init = sysbus_ahci_init; dc->vmsd = &vmstate_sysbus_ahci; dc->props = sysbus_ahci_properties; dc->reset = sysbus_ahci_reset; } static TypeInfo sysbus_ahci_info = { Loading
hw/ide/ahci.h +1 −1 Original line number Diff line number Diff line Loading @@ -332,6 +332,6 @@ typedef struct NCQFrame { void ahci_init(AHCIState *s, DeviceState *qdev, int ports); void ahci_uninit(AHCIState *s); void ahci_reset(void *opaque); void ahci_reset(AHCIState *s); #endif /* HW_IDE_AHCI_H */
hw/ide/ich.c +4 −6 Original line number Diff line number Diff line Loading @@ -84,12 +84,12 @@ static const VMStateDescription vmstate_ahci = { .unmigratable = 1, }; static void pci_ich9_reset(void *opaque) static void pci_ich9_reset(DeviceState *dev) { struct AHCIPCIState *d = opaque; struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev); msi_reset(&d->card); ahci_reset(opaque); ahci_reset(&d->ahci); } static int pci_ich9_ahci_init(PCIDevice *dev) Loading @@ -110,8 +110,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) /* XXX Software should program this register */ d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ qemu_register_reset(pci_ich9_reset, d); msi_init(dev, 0x50, 1, true, false); d->ahci.irq = d->card.irq[0]; Loading Loading @@ -141,7 +139,6 @@ static int pci_ich9_uninit(PCIDevice *dev) d = DO_UPCAST(struct AHCIPCIState, card, dev); msi_uninit(dev); qemu_unregister_reset(pci_ich9_reset, d); ahci_uninit(&d->ahci); return 0; Loading @@ -167,6 +164,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data) k->revision = 0x02; k->class_id = PCI_CLASS_STORAGE_SATA; dc->vmsd = &vmstate_ahci; dc->reset = pci_ich9_reset; } static TypeInfo ich_ahci_info = { Loading