Commit 8a7b5c18 authored by Stefan Hajnoczi's avatar Stefan Hajnoczi
Browse files

Merge remote-tracking branch 'dgibson/tags/ppc-for-2.8-20161115' into staging 



ppc patch queue 2016-11-15

Latest set of ppc and spapr related patches.  Highlights are:
   * More POWER9 instructions
   * Fix some subtle outstanding bugs
   * Add some extra tests

One patch affects bitops.h, so isn't strictly ppc related.

# gpg: Signature made Tue 15 Nov 2016 02:46:48 AM GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* dgibson/tags/ppc-for-2.8-20161115:
  boot-serial-test: Add a test for the powernv machine
  tests: add XSCOM tests for the PowerNV machine
  ppc/pnv: Fix fatal bug on 32-bit hosts
  ppc/pnv: fix xscom address translation for POWER9
  ppc/pnv: add a 'xscom_core_base' field to PnvChipClass
  spapr-vty: Fix bad assert() statement
  FU exceptions should carry a cause (IC)
  spapr: Fix migration of PCI host bridges from qemu-2.7
  target-ppc: Implement bcdctz. instruction
  target-ppc: Implement bcdcfz. instruction
  target-ppc: Implement bcdctn. instruction
  target-ppc: Implement bcdcfn. instruction
  ppc: Remove some stub POWER6 models
  ppc/pnv: fix compile breakage on old gcc
  powernv: CPU compatibility modes don't make sense for powernv
  target-ppc: add vprtyb[w/d/q] instructions
  target-ppc: add vrldnm and vrlwnm instructions
  target-ppc: add vrldnmi and vrlwmi instructions
  bitops: fix rol/ror when shift is zero

Message-id: 1479178144-28153-1-git-send-email-david@gibson.dropbear.id.au
Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
parents 5d0df6de 859c397e

disas/ppc.c

+4 −0
Original line number Diff line number Diff line
@@ -2286,6 +2286,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { 
{ "vrlh",      VX(4,   68), VX_MASK,	PPCVEC,		{ VD, VA, VB } },

{ "vrlw",      VX(4,  132), VX_MASK,	PPCVEC,		{ VD, VA, VB } },

{ "vrsqrtefp", VX(4,  330), VX_MASK,	PPCVEC,		{ VD, VB } },

{ "vrldmi",    VX(4,  197), VX_MASK,    PPCVEC,         { VD, VA, VB } },

{ "vrldnm",    VX(4,  453), VX_MASK,    PPCVEC,         { VD, VA, VB } },

{ "vrlwmi",    VX(4,  133), VX_MASK,    PPCVEC,         { VD, VA, VB} },

{ "vrlwnm",    VX(4,  389), VX_MASK,    PPCVEC,         { VD, VA, VB } },

{ "vsel",      VXA(4,  42), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },

{ "vsl",       VX(4,  452), VX_MASK,	PPCVEC,		{ VD, VA, VB } },

{ "vslb",      VX(4,  260), VX_MASK,	PPCVEC,		{ VD, VA, VB } },

hw/char/spapr_vty.c

+10 −1
Original line number Diff line number Diff line 
#include "qemu/osdep.h"

#include "qemu/error-report.h"

#include "qapi/error.h"

#include "qemu-common.h"

#include "cpu.h"
@@ -37,7 +38,15 @@ static void vty_receive(void *opaque, const uint8_t *buf, int size) 
        qemu_irq_pulse(spapr_vio_qirq(&dev->sdev));

    }

    for (i = 0; i < size; i++) {

        assert((dev->in - dev->out) < VTERM_BUFSIZE);

        if (dev->in - dev->out >= VTERM_BUFSIZE) {

            static bool reported;

            if (!reported) {

                error_report("VTY input buffer exhausted - characters dropped."

                             " (input size = %i)", size);

                reported = true;

            }

            break;

        }

        dev->buf[dev->in++ % VTERM_BUFSIZE] = buf[i];

    }

}

hw/ppc/pnv.c

+9 −7
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 
    CPUState *cs = CPU(DEVICE(pc->threads));

    DeviceClass *dc = DEVICE_GET_CLASS(cs);

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    int smt_threads = ppc_get_compat_smt_threads(cpu);

    int smt_threads = CPU_CORE(pc)->nr_threads;

    CPUPPCState *env = &cpu->env;

    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);

    uint32_t servers_prop[smt_threads];
@@ -206,10 +206,6 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 
    _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",

                       pa_features, sizeof(pa_features))));



    if (cpu->cpu_version) {

        _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version)));

    }



    /* Build interrupt servers properties */

    for (i = 0; i < smt_threads; i++) {

        servers_prop[i] = cpu_to_be32(pc->pir + i);
@@ -525,6 +521,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8E_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->xscom_base = 0x003fc0000000000ull;

    k->xscom_core_base = 0x10000000ull;

    dc->desc = "PowerNV Chip POWER8E";

}
@@ -546,6 +543,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->xscom_base = 0x003fc0000000000ull;

    k->xscom_core_base = 0x10000000ull;

    dc->desc = "PowerNV Chip POWER8";

}
@@ -567,6 +565,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->xscom_base = 0x003fc0000000000ull;

    k->xscom_core_base = 0x10000000ull;

    dc->desc = "PowerNV Chip POWER8NVL";

}
@@ -588,6 +587,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER9_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p9;

    k->xscom_base = 0x00603fc00000000ull;

    k->xscom_core_base = 0x0ull;

    dc->desc = "PowerNV Chip POWER9";

}
@@ -620,7 +620,7 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 
    chip->cores_mask &= pcc->cores_mask;



    /* now that we have a sane layout, let check the number of cores */

    cores_max = hweight_long(chip->cores_mask);

    cores_max = ctpop64(chip->cores_mask);

    if (chip->nr_cores > cores_max) {

        error_setg(errp, "warning: too many cores for chip ! Limit is %d",

                   cores_max);
@@ -695,7 +695,9 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) 
        object_unref(OBJECT(pnv_core));



        /* Each core has an XSCOM MMIO region */

        pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid),

        pnv_xscom_add_subregion(chip,

                                PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,

                                                       core_hwid),

                                &PNV_CORE(pnv_core)->xscom_regs);

        i++;

    }

hw/ppc/pnv_core.c

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "hw/ppc/ppc.h"

#include "hw/ppc/pnv.h"

#include "hw/ppc/pnv_core.h"

#include "hw/ppc/pnv_xscom.h"



static void powernv_cpu_reset(void *opaque)

{

hw/ppc/pnv_lpc.c

+2 −1
Original line number Diff line number Diff line
@@ -23,8 +23,9 @@ 
#include "qapi/error.h"

#include "qemu/log.h"



#include "hw/ppc/pnv_lpc.h"

#include "hw/ppc/pnv.h"

#include "hw/ppc/pnv_lpc.h"

#include "hw/ppc/pnv_xscom.h"

#include "hw/ppc/fdt.h"



#include <libfdt.h>